bioz-firmware-rs/src/ad5940_registers.rs

use bitflags::bitflags;

pub trait Resettable {
    fn reset() -> Self;
    // fn msk() -> u32;
}

#[allow(dead_code)]
pub enum T9CON {
    T9Closed = 1,
    T9Open = 0,
}

impl Resettable for T9CON {
    fn reset() -> Self {
        T9CON::T9Open
    }
    // fn msk() -> u32 {
        // 0b1
    // }
}

#[allow(dead_code)]
pub enum TMUXCON {
    AllOpen = 0b1111,
    T1Closed = 0b0001,
    T2Closed = 0b0010,
    T3Closed = 0b0011,
    T4Closed = 0b0100,
    T5Closed = 0b0101,
    T6Closed = 0b0110,
    T7Closed = 0b0111,
    TR1Closed = 0b1000,
    AllClosed = 0b1001,
}

impl Resettable for TMUXCON {
    fn reset() -> Self {
        TMUXCON::AllOpen
    }
}

#[allow(dead_code)]
pub enum NMUXCON {
    NLClosed = 0b0000,
    N1Closed = 0b0001,
    N2Closed = 0b0010,
    N3Closed = 0b0011,
    N4Closed = 0b0100,
    N5Closed = 0b0101,
    N6Closed = 0b0110,
    N7Closed = 0b0111,
    N9Closed = 0b1001,
    NR1Closed = 0b1010,
    NL1Closed = 0b1011,
    AllOpen = 0b1111,
}

impl Resettable for NMUXCON {
    fn reset() -> Self {
        NMUXCON::AllOpen
    }
}

#[allow(dead_code)]
pub enum PMUXCON {
    PLClosed = 0b0000,
    PR0Closed = 0b0001,
    P2Closed = 0b0010,
    P3Closed = 0b0011,
    P4Closed = 0b0100,
    P5Closed = 0b0101,
    P6Closed = 0b0110,
    P7Closed = 0b0111,
    P9Closed = 0b1001,
    P11Closed = 0b1011,
    PL2Closed = 0b1110,
    AllOpen = 0b1111,
}

impl Resettable for PMUXCON {
    fn reset() -> Self {
        PMUXCON::AllOpen
    }
}

#[allow(dead_code)]
pub enum DMUXCON {
    AllOpen = 0b1111,
    DR0Closed = 0b0001,
    D2Closed = 0b0010,
    D3Closed = 0b0011,
    D4Closed = 0b0100,
    D5Closed = 0b0101,
    D6Closed = 0b0110,
    D7Closed = 0b0111,
    P8Closed = 0b1000,
    AllClosed = 0b1001
}

impl Resettable for DMUXCON {
    fn reset() -> Self {
        DMUXCON::AllOpen
    }
}

#[allow(dead_code)]
#[repr(u32)]
pub enum MUXSELN 
{
    HsTiaNeg = 0b00001,
    LpTiaNeg = 0b00010,
    AIN1    = 0b00101,
}

#[allow(dead_code)]
#[repr(u32)]
pub enum MUXSELP {
    HsTiaPos = 0b00001,
    AIN1    = 0b00101,
}

#[allow(dead_code)]
#[repr(u32)]
pub enum DFTINSEL {
    Sinc2       = 0b00,
    GainOffset  = 0b01,
    AdcRaw      = 0b10
}

impl Resettable for DFTINSEL {
    fn reset() -> Self {
        DFTINSEL::Sinc2
    }
}

#[allow(dead_code)]
#[repr(u32)]
pub enum DFTNUM {
    Num4       = 0b0000,
    Num8       = 0b0001,
    Num16      = 0b0010,
    Num32      = 0b0011,
    Num64      = 0b0100,
    Num128     = 0b0101,
    Num256     = 0b0110,
    Num512     = 0b0111,
    Num1024    = 0b1000,
    Num2048    = 0b1001,
    Num4096    = 0b1010,
    Num8192    = 0b1011,
    Num16384   = 0b1100,
}

impl Resettable for DFTNUM {
    fn reset() -> Self {
        DFTNUM::Num2048
    }
}

#[allow(dead_code)]
pub enum CTIACON {
    C1 = 0,
    C2 = 1 << 0,
    C4 = 1 << 1,
    C8 = 1 << 2,
    C16 = 1 << 3,
    C32 = 1 << 4,
}

impl Resettable for CTIACON {
    fn reset() -> Self {
        CTIACON::C1
    }
}

#[allow(dead_code)]
pub enum RTIACON {
    R200 = 0b0000,
    R1k  = 0b0001,
    R5k  = 0b0010,
    R10k = 0b0011,
    R20k = 0b0100,
    R40k = 0b0101,
    R80k = 0b0110,
    R160k = 0b0111,
    Open = 0b1111,
}

impl Resettable for RTIACON {
    fn reset() -> Self {
        RTIACON::Open
    }
}

#[allow(dead_code)]
pub enum SINC3OSR {
    R5 = 0b00,
    R4 = 0b01,
    R2 = 0b10,
}

impl Resettable for SINC3OSR {
    fn reset() -> Self {
        SINC3OSR::R5
    }
}

#[allow(dead_code)]
pub enum SINC2OSR {
    R22 = 0b0000,
    R44 = 0b0001,
    R89 = 0b0010,
    R178 = 0b0011,
    R267 = 0b0100,
    R533 = 0b0101,
    R640 = 0b0110,
    R667 = 0b0111,
    R800 = 0b1000,
    R889 = 0b1001,
    R1067 = 0b1010,
    R1333 = 0b1011,
}

impl Resettable for SINC2OSR {
    fn reset() -> Self {
        SINC2OSR::R178
    }
}

#[allow(dead_code)]
pub enum ADCSAMPLERATE {
    R800Hz = 1,
    R1_6MHz = 0,
}

impl Resettable for ADCSAMPLERATE {
    fn reset() -> Self {
        ADCSAMPLERATE::R1_6MHz
    }
}

bitflags! {
    // Configuration Register
    // Address 0x00002000, Reset: 0x00080000, Name: AFECON
    #[derive(Clone, Copy)]
    pub struct AFECON: u32 {
        const DACBUFEN = 1 << 21;
        const DACREFEN = 1 << 20;
        const SINC2EN = 1 << 16;
        const DFTEN = 1 << 15;
        const WAVEGENEN = 1 << 14;
        const TEMPCONVEN = 1 << 13;
        const TEMPSENSEN = 1 << 12;
        const TIAEN = 1 << 11;
        const INAMPEN = 1 << 10;
        const EXBUFEN = 1 << 9;
        const ADCCONVEN = 1 << 8;
        const ADCEN = 1 << 7;
        const DACEN = 1 << 6;
        const HSREFDIS = 1 << 5;
    }
}

bitflags! {
    // Waveform Generator Configuration Register
    // Address 0x00002014, Reset: 0x00000030, Name: WGCON
    pub struct WGCON: u32 {
        const reset         = 0x00000030;
        const DACGAINCAL    = 1 << 5;
        const DACOFFSETCAL  = 1 << 4;
        const TYPESEL_DAC   = 0b00 << 1; // Direct DAC
        const TYPESEL_SIN   = 0b10 << 1; // Sinusoidal
        const TYPESEL_TRA   = 0b11 << 1; // Trapezoidal
        const TRAPRSTEN     = 1;
    }
}

bitflags! {
    // Analog Generation Interrupt Register
    // Address 0x0000209C, Reset: 0x00000010, Name: AFEGENINTSTA
    pub struct AFEGENINTSTA: u32 {
        const CUSTOMINT3 = 1 << 3; // General-Purpose Custom Interrupt 3
        const CUSTOMINT2 = 1 << 2; // General-Purpose Custom Interrupt 2
        const CUSTOMINT1 = 1 << 1; // General-Purpose Custom Interrupt 1
        const CUSTOMINT0 = 1 << 0; // General-Purpose Custom Interrupt 0
    }
}

bitflags! {
    // DFT Configuration Register
    // Address 0x000020D0, Reset: 0x00000090, Name: DFTCON
    pub struct DFTCON: u32 {
        const DFTINSEL_SINC2            = 0b00 << 20;
        const DFTINSEL_GAIN_ANDOFFSET   = 0b01 << 20;
        const ADC_RAW                   = 0b10 << 20;
        const DFTNUM_4                  = 0b0000 << 4;
        const DFTNUM_8                  = 0b0001 << 4;
        const DFTNUM_16                 = 0b0010 << 4;
        const DFTNUM_32                 = 0b0011 << 4;
        const DFTNUM_64                 = 0b0100 << 4;
        const DFTNUM_128                = 0b0101 << 4;
        const DFTNUM_256                = 0b0110 << 4;
        const DFTNUM_512                = 0b0111 << 4;
        const DFTNUM_1024               = 0b1000 << 4;
        const DFTNUM_2048               = 0b1001 << 4;
        const DFTNUM_4096               = 0b1010 << 4;
        const DFTNUM_8192               = 0b1011 << 4;
        const DFTNUM_16384              = 0b1100 << 4;
        const HANNINGEN                 = 0b1 << 0;
    }
}

bitflags! {
    // HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER
    // Address 0x00002180, Reset 0x00000037, Name BEFSENCON
    
}

bitflags! {
    // ADC Configuration Register,
    // Address 0x000021A8, Reset: 0x00000000, Name: ADCCON
    pub struct ADCCON: u32 {
        const GNPGA_1_5    = 1 << 16;
        const MUXSELN_TIAN = 0b00001 << 8;
        const MUXSELN_TEMP = 0b01011 << 8;
        const MUXSELP_TIAP = 0b00001;
        const MUXSELP_TEMP = 0b01011;
    }
}