Implemented LP DAC for enabling common-mode during 4-lead measurement.

src/ad5940.rs

@@ -68,6 +68,55 @@ impl SwitchConfig {
     }
 }
 
+#[allow(dead_code)]
+#[derive(Default)]
+pub struct LpConfig {
+    data_reset: Option<bool>,
+    power_enable: Option<bool>,
+    data_6bit: Option<u8>,
+    common_mode_switch: Option<bool>,
+    tia_switches_enabled: Option<u16>,
+    tia_enable: Option<bool>,
+    filter_resistor: Option<TIARF>,
+}
+
+impl LpConfig {
+    pub fn data_reset(&mut self, rsten: bool) -> &mut Self {
+        self.data_reset = Some(rsten);
+        self
+    }
+
+    pub fn power_enable(&mut self, pwden: bool) -> &mut Self {
+        self.power_enable = Some(pwden);
+        self
+    }
+    
+    pub fn data_6bit(&mut self, data: u8) -> &mut Self {
+        self.data_6bit = Some(data & 0x3F);
+        self
+    }
+
+    pub fn common_mode_enable(&mut self, enable: bool) -> &mut Self {
+        self.common_mode_switch = Some(enable);
+        self
+    }
+
+    pub fn tia_switches_enabled(&mut self, enable: u16) -> &mut Self {
+        self.tia_switches_enabled = Some(enable);
+        self
+    }
+
+    pub fn tia_enable(&mut self, enable: bool) -> &mut Self {
+        self.tia_enable = Some(enable);
+        self
+    }
+
+    pub fn filter_resistor(&mut self, tiarf: TIARF) -> &mut Self {
+        self.filter_resistor = Some(tiarf);
+        self
+    }
+}
+
 #[allow(dead_code)]
 #[derive(Default)]
 pub struct DspConfig {
@@ -594,6 +643,59 @@ impl AD5940 {
         Ok(())
     }
 
+    pub async fn apply_lp_config(&mut self, config: &LpConfig) -> Result<(), Error> {
+        // LPDACCON0
+        let mut current = self.read_reg(Register::LPDACCON0).await?;
+
+        if let Some(data_reset) = config.data_reset {
+            current = RSTEN::apply(current, data_reset as u32);
+        }
+
+        if let Some(power_enable) = config.power_enable {
+            current = PWDEN::apply(current, !power_enable as u32);
+        }
+
+        self.write_reg(Register::LPDACCON0, current).await?;
+
+        // LPDACDAT0
+        let mut current = self.read_reg(Register::LPDACDAT0).await?;
+
+        if let Some(data) = config.data_6bit {
+            current = DACIN6::apply(current, data as u32);
+        }
+
+        self.write_reg(Register::LPDACDAT0, current).await?;
+
+        // SWMUX
+        let mut current = self.read_reg(Register::SWMUX).await?;
+
+        if let Some(common_mode_switch) = config.common_mode_switch {
+            current = SWMUX::apply(current, common_mode_switch as u32);
+        }
+
+        self.write_reg(Register::SWMUX, current).await?;
+
+        // LPTIASW0 
+        if let Some(tia_switches_enabled) = config.tia_switches_enabled {
+            self.write_reg(Register::LPTIASW0, tia_switches_enabled as u32).await?;
+        }
+
+        // LPTIACON0
+        let mut current = self.read_reg(Register::LPTIACON0).await?;
+
+        if let Some(tia_enable) = config.tia_enable {
+            current = TIAPDEN::apply(current, !tia_enable as u32);
+        }
+
+        if let Some(tiarf) = config.filter_resistor {
+            current = TIARF::apply(current, tiarf as u32);
+        }
+
+        self.write_reg(Register::LPTIACON0, current).await?;
+
+        Ok(())
+    }
+
     pub async fn apply_dsp_config(&mut self, config: &DspConfig) -> Result<(), Error> {
         // ADCCON
         let mut current = self.read_reg(Register::ADCCON).await?;
@@ -849,6 +951,10 @@ pub enum Register {
     CMDFIFOWRITE = 0x0000_2070, // Command FIFO Write Register
     TEMPSENSDAT = 0x0000_2084, // Temperature Sensor Result Register
     ADCDAT      = 0x0000_2074, // ADC Raw Result Register
+    LPTIASW0    = 0x0000_20E4, // Low power TIA switch configuration
+    LPTIACON0   = 0x0000_20EC, // Low power TIA control bits, Channel 0
+    LPDACDAT0   = 0x0000_2120, // Low power DAC data output Register 
+    LPDACCON0   = 0x0000_2128, // Low power DAC configuration register 
     TEMPSENS    = 0x0000_2174, // Temperature Sensor Configuration Register
     ADCCON      = 0x0000_21A8, // ADC Configuration Register
     SEQ0INFO    = 0x0000_21CC, // Sequence 0 Information Register
@@ -859,6 +965,7 @@ pub enum Register {
     AFEGENINTSTA = 0x0000_209C, // Analog Generation Interrupt Register
     CMDFIFOWADDR = 0x0000_21D4, // Command FIFO Write Address Register
     PMBW        = 0x0000_22F0, // Power Mode Configuration Register
+    SWMUX       = 0x0000_235C, // Common-mode switch mux select register 
     INTCFLAG0   = 0x0000_3010, // Interrupt Control Flag 0 Register
     INTCFLAG1   = 0x0000_3014, // Interrupt Control Flag 1 Register
     OSCCON      = 0x0000_0A10, // Oscillator Control Register