mirror of
https://github.com/hubaldv/bioz-firmware-rs.git
synced 2026-03-10 00:00:30 +00:00
988 lines
32 KiB
Rust
988 lines
32 KiB
Rust
use defmt::*;
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use embassy_stm32::{gpio::Output, mode::Blocking, spi::Spi, spi::Error};
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use embassy_time::Timer;
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use heapless::LinearMap;
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use crate::ad5940_registers::*;
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#[allow(dead_code)]
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#[derive(Default)]
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pub struct ClkConfig {
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adcclkdiv: Option<ADCCLKDIV>,
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sysclkdiv: Option<SYSCLKDIV>,
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clk32mhzen: Option<CLK32MHZEN>,
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}
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impl ClkConfig {
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pub fn adcclkdiv(mut self, adcclkdiv: ADCCLKDIV) -> Self {
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self.adcclkdiv = Some(adcclkdiv);
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self
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}
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pub fn sysclkdiv(mut self, sysclkdiv: SYSCLKDIV) -> Self {
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self.sysclkdiv = Some(sysclkdiv);
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self
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}
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pub fn clk32mhzen(mut self, clk32mhzen: CLK32MHZEN) -> Self {
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self.clk32mhzen = Some(clk32mhzen);
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self
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}
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}
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#[allow(dead_code)]
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#[derive(Default)]
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pub struct SwitchConfig {
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t9con: Option<T9CON>,
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tmuxcon: Option<TMUXCON>,
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nmuxcon: Option<NMUXCON>,
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pmuxcon: Option<PMUXCON>,
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dmuxcon: Option<DMUXCON>,
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}
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impl SwitchConfig {
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pub fn t9con(mut self, t9con: T9CON) -> Self {
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self.t9con = Some(t9con);
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self
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}
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pub fn tmuxcon(mut self, tmuxcon: TMUXCON) -> Self {
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self.tmuxcon = Some(tmuxcon);
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self
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}
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pub fn nmuxcon(mut self, nmuxcon: NMUXCON) -> Self {
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self.nmuxcon = Some(nmuxcon);
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self
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}
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pub fn pmuxcon(mut self, pmuxcon: PMUXCON) -> Self {
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self.pmuxcon = Some(pmuxcon);
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self
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}
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pub fn dmuxcon(mut self, dmuxcon: DMUXCON) -> Self {
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self.dmuxcon = Some(dmuxcon);
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self
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}
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}
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#[allow(dead_code)]
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#[derive(Default)]
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pub struct LpConfig {
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data_reset: Option<bool>,
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power_enable: Option<bool>,
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data_6bit: Option<u8>,
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common_mode_switch: Option<bool>,
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tia_switches_enabled: Option<u16>,
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tia_enable: Option<bool>,
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filter_resistor: Option<TIARF>,
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}
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impl LpConfig {
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pub fn data_reset(&mut self, rsten: bool) -> &mut Self {
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self.data_reset = Some(rsten);
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self
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}
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pub fn power_enable(&mut self, pwden: bool) -> &mut Self {
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self.power_enable = Some(pwden);
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self
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}
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pub fn data_6bit(&mut self, data: u8) -> &mut Self {
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self.data_6bit = Some(data & 0x3F);
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self
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}
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pub fn common_mode_enable(&mut self, enable: bool) -> &mut Self {
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self.common_mode_switch = Some(enable);
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self
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}
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pub fn tia_switches_enabled(&mut self, enable: u16) -> &mut Self {
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self.tia_switches_enabled = Some(enable);
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self
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}
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pub fn tia_enable(&mut self, enable: bool) -> &mut Self {
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self.tia_enable = Some(enable);
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self
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}
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pub fn filter_resistor(&mut self, tiarf: TIARF) -> &mut Self {
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self.filter_resistor = Some(tiarf);
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self
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}
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}
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#[allow(dead_code)]
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#[derive(Default)]
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pub struct DspConfig {
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pub gnpgain: Option<GNPGAIN>,
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muxseln: Option<MUXSELN>,
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muxselp: Option<MUXSELP>,
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ctiacon: Option<CTIACON>,
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rtiacon: Option<RTIACON>,
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sinc3osr: Option<SINC3OSR>,
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sinc2osr: Option<SINC2OSR>,
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adcsamplerate: Option<ADCSAMPLERATE>,
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dftin: Option<DFTINSEL>,
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dftnum: Option<DFTNUM>,
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hanning: Option<bool>,
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pub fsys: Option<u32>,
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pub fadc: Option<u32>,
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ratio_sys2adc_clk: Option<f32>,
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}
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impl DspConfig {
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pub fn gnpgain(&mut self, gnpgain: GNPGAIN) -> &mut Self {
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self.gnpgain = Some(gnpgain);
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self
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}
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pub fn adc_mux_n(&mut self, muxseln: MUXSELN) -> &mut Self {
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self.muxseln = Some(muxseln);
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self
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}
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pub fn adc_mux_p(&mut self, muxselp: MUXSELP) -> &mut Self {
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self.muxselp = Some(muxselp);
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self
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}
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pub fn ctiacon(&mut self, ctiacon: CTIACON) -> &mut Self {
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self.ctiacon = Some(ctiacon);
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self
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}
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pub fn rtiacon(&mut self, rtiacon: RTIACON) -> &mut Self {
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self.rtiacon = Some(rtiacon);
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self
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}
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pub fn sinc3osr(&mut self, sinc3osr: SINC3OSR) -> &mut Self {
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self.sinc3osr = Some(sinc3osr);
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self
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}
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pub fn sinc2osr(&mut self, sinc2osr: SINC2OSR) -> &mut Self {
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self.sinc2osr = Some(sinc2osr);
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self
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}
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pub fn adcsamplerate(&mut self, adcsamplerate: ADCSAMPLERATE) -> &mut Self {
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self.adcsamplerate = Some(adcsamplerate);
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self
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}
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pub fn dftin_sel(&mut self, dftin: DFTINSEL) -> &mut Self {
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self.dftin = Some(dftin);
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self
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}
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pub fn dftnum(&mut self, dftnum: DFTNUM) -> &mut Self {
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self.dftnum = Some(dftnum);
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self
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}
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pub fn hanning(&mut self, hanning: bool) -> &mut Self {
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self.hanning = Some(hanning);
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self
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}
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pub fn set_clks(&mut self, fsys: u32, fadc: u32) -> &mut Self {
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self.fsys = Some(fsys);
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self.fadc = Some(fadc);
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self.ratio_sys2adc_clk = Some(fsys as f32 / fadc as f32);
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self
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}
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}
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#[allow(dead_code)]
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#[derive(Default)]
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pub struct SramConfig {
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datafifosrcsel: Option<DATAFIFOSRCSEL>,
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datafifoen: Option<DATAFIFOEN>,
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data_mem_size: Option<DATA_MEM_SEL>,
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cmd_mem_mode: Option<CMDMEMMDE>,
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cmd_mem_size: Option<CMD_MEM_SEL>,
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}
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impl SramConfig {
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pub fn datafifosrcsel(&mut self, datafifosrcsel: DATAFIFOSRCSEL) -> &mut Self {
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self.datafifosrcsel = Some(datafifosrcsel);
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self
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}
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pub fn datafifoen(&mut self, datafifoen: DATAFIFOEN) -> &mut Self {
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self.datafifoen = Some(datafifoen);
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self
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}
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pub fn data_size(&mut self, data_mem_size: DATA_MEM_SEL) -> &mut Self {
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self.data_mem_size = Some(data_mem_size);
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self
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}
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pub fn cmd_mode(&mut self, cmd_mem_mode: CMDMEMMDE) -> &mut Self {
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self.cmd_mem_mode = Some(cmd_mem_mode);
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self
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}
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pub fn cmd_size(&mut self, cmd_mem_size: CMD_MEM_SEL) -> &mut Self {
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self.cmd_mem_size = Some(cmd_mem_size);
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self
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}
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}
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pub struct Sequencer {
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}
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impl Sequencer {
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pub fn new() -> Self {
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Sequencer {}
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}
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pub async fn configure(&mut self, ad5940: &mut AD5940) -> Result<(), Error> {
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// Configure the sequencer here if needed
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// This is a placeholder for future sequencer configuration logic
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Ok(())
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}
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}
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pub struct AD5940 {
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spi: Spi<'static, Blocking>,
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cs: Output<'static>,
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rst: Output<'static>,
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seq_enabled: bool,
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pub seq_len: usize,
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pub seq_buffer: [u32; 500],
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pub seq_gen_db: LinearMap<Register, u32, 16>,
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}
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impl AD5940 {
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pub fn new(spi: Spi<'static, Blocking>, cs: Output<'static>, rst: Output<'static>) -> Self {
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AD5940 {
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spi,
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cs,
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rst,
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seq_enabled: false,
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seq_len: 0,
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seq_buffer: [0; 500],
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seq_gen_db: LinearMap::new(),
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}
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}
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pub async fn reset(&mut self) -> Result<(), Error> {
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self.rst.set_low();
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Timer::after_millis(1).await;
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self.rst.set_high();
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Ok(())
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}
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pub async fn read_reg(&mut self, address: Register) -> Result<u32, Error> {
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if self.seq_enabled {
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self.sequencer_read_register(address).await
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} else {
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self.read_reg_raw(address as u16).await
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}
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}
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pub async fn read_reg_raw(&mut self, address: u16) -> Result<u32, Error> {
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// Write address command
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_SETADDR as u8])?;
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self.spi.blocking_write(&[address as u16])?;
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self.cs.set_high();
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// Wait after cs is high
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Timer::after_nanos(80).await;
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// Read command
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_READREG as u8])?;
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self.spi.blocking_write(&[0 as u8])?; // Dummy byte
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let result: u32;
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if (address as u32) >= 0x1000 && (address as u32) <= 0x3014 {
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let mut data = [0u8; 4];
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self.spi.blocking_read(&mut data)?;
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result = u32::from_be_bytes(data);
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} else {
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let mut data = [0u8; 2];
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self.spi.blocking_read(&mut data)?;
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result = u16::from_be_bytes(data) as u32;
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}
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// let mut data = [0u8; 5]; // First byte dummy, then four data bytes
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// self.spi.blocking_read(&mut data)?;
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self.cs.set_high();
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Ok(result)
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}
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pub async fn write_reg(&mut self, address: Register, value: u32) -> Result<(), Error> {
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if self.seq_enabled {
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self.sequencer_write_register(address, value).await
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} else {
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self.write_reg_raw(address as u16, value).await
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}
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}
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pub async fn write_reg_raw(&mut self, address: u16, value: u32) -> Result<(), Error> {
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// Write address command
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_SETADDR as u8])?;
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self.spi.blocking_write(&[address as u16])?;
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self.cs.set_high();
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// Wait after cs is high
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Timer::after_nanos(80).await;
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// Write value command
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_WRITEREG as u8])?;
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if (address>=0x1000) && (address<=0x3014) {
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self.spi.blocking_write(&[value])?;
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} else {
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self.spi.blocking_write(&[value as u16])?;
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}
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self.cs.set_high();
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Ok(())
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}
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pub async fn read_fifo(&mut self, buf: &mut [u32]) -> Result<(), Error> {
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if buf.len() < 3 {
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_SETADDR as u8])?;
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self.spi.blocking_write(&[Register::DATAFIFORD as u16])?;
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self.cs.set_high();
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// Wait after cs is high
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Timer::after_nanos(80).await;
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for i in 0..buf.len() {
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_READREG as u8])?;//Write Host status/Don't care
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self.spi.blocking_write(&[0 as u8])?;//Write Host status/Don't care
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let mut byte = [0u32];
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self.spi.blocking_read(&mut byte)?;
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buf[i] = byte[0];
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self.cs.set_high();
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// Wait after cs is high
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Timer::after_nanos(80).await;
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}
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} else {
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self.cs.set_low();
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self.spi.blocking_write(&[Command::SPICMD_READFIFO as u8])?;
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// 6 dummy writes
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for _ in 0..6 {
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self.spi.blocking_write(&[0u8])?;
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}
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// Read all but last 2 elements
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for i in 0..buf.len()-2 {
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let mut byte = [0u32];
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self.spi.blocking_read(&mut byte)?;
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buf[i] = byte[0];
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}
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// Read last 2 elements with transfer
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let mut bytes = [0u32; 2];
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self.spi.blocking_transfer(&mut bytes, &mut [0x4444_4444, 0x4444_4444])?;
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buf[buf.len()-2] = bytes[0];
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buf[buf.len()-1] = bytes[1];
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self.cs.set_high();
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}
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Ok(())
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}
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pub async fn system_init(&mut self) -> Result<(), Error> {
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// See table 14
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self.write_reg_raw(0x0908, 0x02C9).await?;
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self.write_reg_raw(0x0C08, 0x206C).await?;
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self.write_reg_raw(0x21F0, 0x0010).await?; // REPEATADCCNV
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self.write_reg_raw(0x0410, 0x02C9).await?; // CMDDATACON
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self.write_reg_raw(0x0A28, 0x0009).await?; // EI2CON
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self.write_reg_raw(0x238C, 0x0104).await?;
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self.write_reg_raw(0x0A04, 0x4859).await?; // PWRKEY
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self.write_reg_raw(0x0A04, 0xF27B).await?; // PWRKEY
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self.write_reg_raw(0x0A00, 0x8009).await?; // PWRMOD
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self.write_reg_raw(0x22F0, 0x0000).await?; // PMBW
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// According to library
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self.write_reg_raw(0x2230, 0xDE87A5AF).await?;
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self.write_reg_raw(0x2250, 0x103F).await?;
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self.write_reg_raw(0x2230, 0xDE87A5A0).await?;
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self.write_reg_raw(0x22B0, 0x203C).await?;
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Ok(())
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}
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pub async fn sequencer_enable(&mut self, enabled: bool) {
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self.seq_enabled = enabled;
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if enabled {
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self.seq_len = 0;
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}
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}
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async fn sequencer_read_register(&mut self, address: Register) -> Result<u32, Error> {
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if address as u32 > 0x21FF {
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error!("Sequencer read address out of range: 0x{:04X}", address as u32);
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}
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// Read from sequencer database, if not present read default (often default) from hardware
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if let Some(value) = self.seq_gen_db.get(&address) {
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Ok(*value)
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} else {
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self.read_reg_raw(address as u16).await
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}
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}
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async fn sequencer_write_register(&mut self, address: Register, value: u32) -> Result<(), Error> {
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if address as u32 > 0x21FF {
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error!("Sequencer write address out of range: 0x{:04X}", address as u32);
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}
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// Update or put in sequencer database
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if self.seq_gen_db.contains_key(&address) {
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*self.seq_gen_db.get_mut(&address).unwrap() = value;
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} else {
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self.seq_gen_db.insert(address, value).unwrap();
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}
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// Place into buffer
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let cmd = 0b1 << 31 | (((address as u32) >> 2) & 0x7F) << 24 | (value & 0xFF_FFFF);
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self.sequencer_insert(cmd).await;
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return Ok(())
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}
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pub async fn sequencer_wait(&mut self, cycles: u32) {
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if cycles > 0x3FFF_FFFF {
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error!("Sequencer wait cycles out of range: {}", cycles);
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return;
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}
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let cmd = 0b00 << 30 | 0x0000_0000 | cycles & 0x3FFF_FFFF;
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self.sequencer_insert(cmd).await;
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}
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pub async fn sequencer_trigger_interrupt(&mut self, int: AFEGENINTSTA) {
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let cmd = 0x10 | int.bits();
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self.sequencer_write_register(Register::AFEGENINTSTA, cmd).await.unwrap();
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}
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async fn sequencer_insert(&mut self, cmd: u32) {
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if self.seq_len >= self.seq_buffer.len() {
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error!("Sequencer buffer full, cannot insert command: 0x{:08X}", cmd);
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return;
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}
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self.seq_buffer[self.seq_len] = cmd;
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self.seq_len += 1;
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}
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pub async fn sequencer_cmd_write(&mut self, mut start_address: u32) {
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// let start_address = 3000 >> 2;
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let mut counter = 0;
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start_address &= 0x7FF; // Ensure start address is within bounds
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while counter < self.seq_len {
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self.write_reg(Register::CMDFIFOWADDR, start_address + counter as u32).await.unwrap();
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self.write_reg(Register::CMDFIFOWRITE, self.seq_buffer[counter as usize]).await.unwrap();
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counter += 1;
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|
}
|
|
}
|
|
|
|
pub async fn sequencer_info_configure(&mut self, seq: u8, length: usize, start_address: u32) {
|
|
let cmd = (length as u32 & 0x7FF) << 16 | (start_address & 0x7FF);
|
|
|
|
match seq {
|
|
0 => self.write_reg(Register::SEQ0INFO, cmd).await.unwrap(),
|
|
1 => self.write_reg(Register::SEQ1INFO, cmd).await.unwrap(),
|
|
2 => self.write_reg(Register::SEQ2INFO, cmd).await.unwrap(),
|
|
3 => self.write_reg(Register::SEQ3INFO, cmd).await.unwrap(),
|
|
_ => {
|
|
error!("Sequencers from 0 till 3 are allows, now: seq={}", seq);
|
|
},
|
|
}
|
|
}
|
|
|
|
pub async fn sequencer_trigger(&mut self, seq: u8) {
|
|
// Trigger the sequencer
|
|
match seq {
|
|
0 => self.write_reg(Register::TRIGSEQ, 1 << 0).await.unwrap(),
|
|
1 => self.write_reg(Register::TRIGSEQ, 1 << 1).await.unwrap(),
|
|
2 => self.write_reg(Register::TRIGSEQ, 1 << 2).await.unwrap(),
|
|
3 => self.write_reg(Register::TRIGSEQ, 1 << 3).await.unwrap(),
|
|
_ => {
|
|
error!("Sequencers from 0 till 3 are allows, now: seq={}", seq);
|
|
},
|
|
}
|
|
}
|
|
|
|
pub async fn sequencer_calculate_wait_time(&mut self, config: &DspConfig) -> Option<u32> {
|
|
let mut wait_time = 1;
|
|
|
|
let sinc3_table = [5, 4, 2];
|
|
let sinc2_table = [22, 44, 89, 178, 267, 533, 640, 667, 800, 889, 1067, 1333];
|
|
|
|
match config.dftin {
|
|
Some(DFTINSEL::Sinc2) => {
|
|
if let Some(sinc3osr) = config.sinc3osr {
|
|
wait_time *= sinc3_table[sinc3osr as usize];
|
|
} else {
|
|
return None; // Sinc2 requires sinc3osr to be set
|
|
};
|
|
|
|
if let Some(sinc2osr) = config.sinc2osr {
|
|
wait_time *= sinc2_table[sinc2osr as usize];
|
|
} else {
|
|
return None; // Sinc2 requires sinc2osr to be set
|
|
};
|
|
}
|
|
Some(DFTINSEL::GainOffset) => {
|
|
if let Some(sinc3osr) = config.sinc3osr {
|
|
wait_time *= sinc3_table[sinc3osr as usize];
|
|
} else {
|
|
return None; // Sinc2 requires sinc3osr to be set
|
|
};
|
|
}
|
|
Some(DFTINSEL::AdcRaw) => {
|
|
}
|
|
None => {
|
|
return None;
|
|
}
|
|
}
|
|
|
|
// Calculate wait time based on DFTNUM
|
|
if let Some(dftnum) = config.dftnum {
|
|
let samples_per_dft = 1 << (dftnum as u32 + 2);
|
|
wait_time *= samples_per_dft;
|
|
} else {
|
|
return None; // DFTNUM must be set
|
|
}
|
|
|
|
// When ACLK = 16MHz, ADC samplerate is 800kHz
|
|
// When ACLK = 32MHz, ADC samplerate is 1.6MHz
|
|
// If ACLK == SYSCLK --> Always per ADC sample 20 cycles
|
|
// If ACLK != SYSCLK --> Always per ADC sample 20*(SYSCLK/ACLK) cycles
|
|
// When SYSCLK is lower, the wait cycles to wait are less becasuse the ADC samples at higher rate
|
|
wait_time *= 20;
|
|
|
|
if let Some(ratio) = config.ratio_sys2adc_clk {
|
|
wait_time = (wait_time as f32 * ratio) as u32;
|
|
} else {
|
|
return None; // Ratio must be set
|
|
}
|
|
|
|
Some(wait_time)
|
|
}
|
|
|
|
pub async fn apply_switch_config(&mut self, config: SwitchConfig) -> Result<(), Error> {
|
|
// SWCON
|
|
let mut current = self.read_reg(Register::SWCON).await?;
|
|
|
|
if let Some(t9con) = config.t9con {
|
|
current = T9CON::apply(current, t9con as u32);
|
|
}
|
|
|
|
if let Some(tmuxcon) = config.tmuxcon {
|
|
current = TMUXCON::apply(current, tmuxcon as u32);
|
|
}
|
|
|
|
if let Some(nmuxcon) = config.nmuxcon {
|
|
current = NMUXCON::apply(current, nmuxcon as u32);
|
|
}
|
|
|
|
if let Some(pmuxcon) = config.pmuxcon {
|
|
current = PMUXCON::apply(current, pmuxcon as u32);
|
|
}
|
|
|
|
if let Some(dmuxcon) = config.dmuxcon {
|
|
current = DMUXCON::apply(current, dmuxcon as u32);
|
|
}
|
|
|
|
self.write_reg(Register::SWCON, current).await?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn apply_clk_config(&mut self, config: &ClkConfig) -> Result<(), Error> {
|
|
// PMBW
|
|
let mut current = self.read_reg(Register::PMBW).await?;
|
|
current |= 0b1;
|
|
self.write_reg(Register::PMBW, current).await?;
|
|
|
|
// CLKCON0
|
|
let mut current = self.read_reg(Register::CLKCON0).await?;
|
|
|
|
if let Some(adcclkdiv) = config.adcclkdiv {
|
|
current = ADCCLKDIV::apply(current, adcclkdiv as u32);
|
|
}
|
|
|
|
if let Some(sysclkdiv) = config.sysclkdiv {
|
|
current = SYSCLKDIV::apply(current, sysclkdiv as u32);
|
|
}
|
|
self.write_reg(Register::CLKCON0, current).await?;
|
|
|
|
// HSOSCCON
|
|
let mut current = self.read_reg(Register::HSOSCCON).await?;
|
|
if let Some(clk32mhzen) = config.clk32mhzen {
|
|
current = CLK32MHZEN::apply(current, clk32mhzen as u32);
|
|
}
|
|
|
|
self.write_reg(Register::HSOSCCON, current).await?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn apply_lp_config(&mut self, config: &LpConfig) -> Result<(), Error> {
|
|
// LPDACCON0
|
|
let mut current = self.read_reg(Register::LPDACCON0).await?;
|
|
|
|
if let Some(data_reset) = config.data_reset {
|
|
current = RSTEN::apply(current, data_reset as u32);
|
|
}
|
|
|
|
if let Some(power_enable) = config.power_enable {
|
|
current = PWDEN::apply(current, !power_enable as u32);
|
|
}
|
|
|
|
self.write_reg(Register::LPDACCON0, current).await?;
|
|
|
|
// LPDACDAT0
|
|
let mut current = self.read_reg(Register::LPDACDAT0).await?;
|
|
|
|
if let Some(data) = config.data_6bit {
|
|
current = DACIN6::apply(current, data as u32);
|
|
}
|
|
|
|
self.write_reg(Register::LPDACDAT0, current).await?;
|
|
|
|
// SWMUX
|
|
let mut current = self.read_reg(Register::SWMUX).await?;
|
|
|
|
if let Some(common_mode_switch) = config.common_mode_switch {
|
|
current = SWMUX::apply(current, common_mode_switch as u32);
|
|
}
|
|
|
|
self.write_reg(Register::SWMUX, current).await?;
|
|
|
|
// LPTIASW0
|
|
if let Some(tia_switches_enabled) = config.tia_switches_enabled {
|
|
self.write_reg(Register::LPTIASW0, tia_switches_enabled as u32).await?;
|
|
}
|
|
|
|
// LPTIACON0
|
|
let mut current = self.read_reg(Register::LPTIACON0).await?;
|
|
|
|
if let Some(tia_enable) = config.tia_enable {
|
|
current = TIAPDEN::apply(current, !tia_enable as u32);
|
|
}
|
|
|
|
if let Some(tiarf) = config.filter_resistor {
|
|
current = TIARF::apply(current, tiarf as u32);
|
|
}
|
|
|
|
self.write_reg(Register::LPTIACON0, current).await?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn apply_dsp_config(&mut self, config: &DspConfig) -> Result<(), Error> {
|
|
// ADCCON
|
|
let mut current = self.read_reg(Register::ADCCON).await?;
|
|
|
|
if let Some(gnpgain) = config.gnpgain {
|
|
current = GNPGAIN::apply(current, gnpgain as u32);
|
|
}
|
|
if let Some(muxseln) = config.muxseln {
|
|
current = MUXSELN::apply(current, muxseln as u32);
|
|
}
|
|
if let Some(muxselp) = config.muxselp {
|
|
current = MUXSELP::apply(current, muxselp as u32);
|
|
}
|
|
|
|
self.write_reg(Register::ADCCON, current).await?;
|
|
|
|
// HSRTIACON
|
|
let mut current = self.read_reg(Register::HSRTIACON).await?;
|
|
|
|
if let Some(ctiacon) = config.ctiacon {
|
|
current = CTIACON::apply(current, ctiacon as u32);
|
|
}
|
|
|
|
if let Some(rtiacon) = config.rtiacon {
|
|
current = RTIACON::apply(current, rtiacon as u32);
|
|
}
|
|
|
|
self.write_reg(Register::HSRTIACON, current).await?;
|
|
|
|
// ADCFILTERCON
|
|
let mut current = self.read_reg(Register::ADCFILTERCON).await?;
|
|
|
|
if let Some(sinc3osr) = config.sinc3osr{
|
|
current = SINC3OSR::apply(current, sinc3osr as u32);
|
|
}
|
|
|
|
if let Some(sinc2osr) = config.sinc2osr {
|
|
current = SINC2OSR::apply(current, sinc2osr as u32);
|
|
}
|
|
|
|
if let Some(adcsamplerate) = config.adcsamplerate {
|
|
current = ADCSAMPLERATE::apply(current, adcsamplerate as u32);
|
|
}
|
|
|
|
self.write_reg(Register::ADCFILTERCON, current).await?;
|
|
|
|
// DFTCON
|
|
let mut current = self.read_reg(Register::DFTCON).await?;
|
|
|
|
if let Some(dftin) = config.dftin {
|
|
current = DFTINSEL::apply(current, dftin as u32);
|
|
}
|
|
if let Some(dftnum) = config.dftnum {
|
|
current = DFTNUM::apply(current, dftnum as u32);
|
|
}
|
|
if let Some(hanning) = config.hanning {
|
|
current = HANNING::apply(current, hanning as u32);
|
|
}
|
|
self.write_reg(Register::DFTCON, current).await?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn afecon(&mut self, ctr: AFECON, state: bool) {
|
|
let reg = self.read_reg(Register::AFECON).await.unwrap();
|
|
let mut reg = AFECON::from_bits_truncate(reg);
|
|
|
|
let flags = [
|
|
AFECON::DACBUFEN,
|
|
AFECON::DACREFEN,
|
|
AFECON::SINC2EN,
|
|
AFECON::DFTEN,
|
|
AFECON::WAVEGENEN,
|
|
AFECON::TEMPCONVEN,
|
|
AFECON::TEMPSENSEN,
|
|
AFECON::TIAEN,
|
|
AFECON::INAMPEN,
|
|
AFECON::EXBUFEN,
|
|
AFECON::ADCCONVEN,
|
|
AFECON::ADCEN,
|
|
AFECON::DACEN,
|
|
AFECON::HSREFDIS,
|
|
];
|
|
|
|
for &flag in flags.iter() {
|
|
if ctr.contains(flag) {
|
|
reg = if state {
|
|
reg | flag
|
|
} else {
|
|
reg & !flag
|
|
};
|
|
}
|
|
}
|
|
|
|
self.write_reg(Register::AFECON, reg.bits()).await.unwrap();
|
|
}
|
|
|
|
pub async fn wgfcw(&mut self, frequency: u32) {
|
|
let sinefcw = (frequency as f64) * (1_073_741_824.0 / 16_000_000.0);
|
|
let sinefcw = 0x00FFFFFF & sinefcw as u32;
|
|
self.write_reg(Register::WGFCW, sinefcw).await.unwrap();
|
|
}
|
|
|
|
pub async fn apply_sram_config(&mut self, config: SramConfig) -> Result<(), Error> {
|
|
// Disable sequencer
|
|
self.write_reg(Register::SEQCON, 0x0000_0002).await?;
|
|
|
|
// Reset SEQCON
|
|
self.write_reg(Register::SEQCNT, 0x0000_0001).await?;
|
|
|
|
// FIFICON
|
|
let mut current_fifocon = self.read_reg(Register::FIFOCON).await?;
|
|
if let Some(datafifosrcsel) = config.datafifosrcsel {
|
|
current_fifocon = DATAFIFOSRCSEL::apply(current_fifocon, datafifosrcsel as u32);
|
|
}
|
|
current_fifocon &= !(0b1 << 11); // Disable FIFO
|
|
self.write_reg(Register::FIFOCON, current_fifocon).await?;
|
|
|
|
// CMDDATACON
|
|
let mut current = self.read_reg(Register::CMDDATACON).await?;
|
|
if let Some(size) = config.data_mem_size {
|
|
current = DATA_MEM_SEL::apply(current, size as u32);
|
|
}
|
|
if let Some(mode) = config.cmd_mem_mode {
|
|
current = CMDMEMMDE::apply(current, mode as u32);
|
|
}
|
|
if let Some(size) = config.cmd_mem_size {
|
|
current = CMD_MEM_SEL::apply(current, size as u32);
|
|
}
|
|
self.write_reg(Register::CMDDATACON, current).await?;
|
|
|
|
// Enable FIFO
|
|
current_fifocon |= 0b1 << 11; // Enable FIFO
|
|
self.write_reg(Register::FIFOCON, current_fifocon).await?;
|
|
|
|
// Enable sequencer
|
|
self.write_reg(Register::SEQCON, 0x0000_0003).await?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn get_chipid(&mut self) -> u16 {
|
|
self.read_reg(Register::CHIPID).await.unwrap() as u16
|
|
}
|
|
|
|
pub async fn get_adiid(&mut self) ->
|
|
u16 {
|
|
self.read_reg(Register::ADIID).await.unwrap() as u16
|
|
}
|
|
|
|
pub async fn init_temperature(&mut self) -> Result<(), Error> {
|
|
// AFECON:
|
|
self.afecon(AFECON::TEMPSENSEN | AFECON::ADCEN, true).await;
|
|
|
|
// ADCCON
|
|
let config_adccon = ADCCON::GNPGA_1_5.bits() | ADCCON::MUXSELN_TEMP.bits() | ADCCON::MUXSELP_TEMP.bits();
|
|
self.write_reg(Register::ADCCON, config_adccon).await?;
|
|
|
|
// AFECON - start conversion
|
|
self.afecon(AFECON::TEMPCONVEN | AFECON::ADCCONVEN, true).await;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn get_temperature(&mut self) -> Result<f32, Error> {
|
|
// See page 57 of the datasheet for temperature calculation
|
|
let pga_gain = 1.5;
|
|
let k = 8.13;
|
|
|
|
let mut tempsensdat0: u32 = self.read_reg(Register::TEMPSENSDAT).await?;
|
|
tempsensdat0 &= 0x0000FFFF;
|
|
|
|
Ok((tempsensdat0 as f32/(pga_gain * k)) - 273.15)
|
|
}
|
|
|
|
pub async fn get_fifo_count(&mut self) -> Result<u32, Error> {
|
|
let data = self.read_reg(Register::FIFOCNTSTA).await?;
|
|
Ok((data >> 16) & 0x7FF)
|
|
}
|
|
|
|
pub async fn clear_and_enable_fifo(&mut self) -> Result<(), Error> {
|
|
let mut fifocon = self.read_reg(Register::FIFOCON).await?;
|
|
fifocon = DATAFIFOEN::apply(fifocon, DATAFIFOEN::FIFOisReset as u32); // Disable FIFO
|
|
self.write_reg(Register::FIFOCON, fifocon).await?;
|
|
|
|
fifocon = DATAFIFOEN::apply(fifocon, DATAFIFOEN::Normal as u32); // Enable FIFO
|
|
self.write_reg(Register::FIFOCON, fifocon).await?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn init_waveform(&mut self) -> Result<(), Error> {
|
|
// Set frequency
|
|
let freq: u32 = 1000;
|
|
self.wgfcw(freq).await;
|
|
|
|
// Init amplitude
|
|
let wg_amplitude = 2047; // 2047 is the maximum amplitude for a 12-bit DAC --> 1.62V peak-to-peak
|
|
self.write_reg(Register::WGAMPLITUDE, wg_amplitude).await?;
|
|
|
|
// WGCON, enable waveform generator and set to sinusoidal, NO DACCAL
|
|
let config_wgcon = WGCON::TYPESEL_SIN.bits();
|
|
self.write_reg(Register::WGCON, config_wgcon).await?;
|
|
|
|
// SWCON - set up switch matri
|
|
let switch_config = SwitchConfig::default()
|
|
.nmuxcon(NMUXCON::N2Closed)
|
|
.pmuxcon(PMUXCON::P11Closed)
|
|
.dmuxcon(DMUXCON::D5Closed);
|
|
self.apply_switch_config(switch_config).await?;
|
|
|
|
// AFECON:
|
|
self.afecon(
|
|
AFECON::DACREFEN
|
|
| AFECON::EXBUFEN
|
|
| AFECON::INAMPEN
|
|
| AFECON::DACEN
|
|
| AFECON::WAVEGENEN,
|
|
true,
|
|
)
|
|
.await;
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
#[allow(dead_code)]
|
|
#[allow(non_camel_case_types)]
|
|
#[repr(u8)]
|
|
enum Command {
|
|
SPICMD_SETADDR = 0x20,
|
|
SPICMD_READREG = 0x6D,
|
|
SPICMD_WRITEREG = 0x2D,
|
|
SPICMD_READFIFO = 0x5F,
|
|
}
|
|
|
|
#[allow(dead_code)]
|
|
#[allow(non_camel_case_types)]
|
|
#[repr(u16)]
|
|
#[derive(Clone, Copy, Eq, PartialEq, Debug, defmt::Format)]
|
|
pub enum Register {
|
|
ADIID = 0x0000_0400, // Analog Devices Inc., identification register
|
|
CHIPID = 0x0000_0404, // Chip identification register
|
|
TRIGSEQ = 0x0000_0430, // Trigger Sequencer Register
|
|
AFECON = 0x0000_2000, // Configuration Register
|
|
SEQCON = 0x0000_2004, // Sequencer Configuration Register
|
|
FIFOCON = 0x0000_2008, // FIFO Configuration Register
|
|
SWCON = 0x0000_200C, // Switch Matrix Configuration Register
|
|
WGCON = 0x0000_2014, // Waveform Generator Configuration Register
|
|
WGFCW = 0x0000_2030, // Waveform Generator, Sinusoid Frequency Control Word Register
|
|
WGAMPLITUDE = 0x0000_203C, // Waveform Generator, Sinusoid Amplitude Register
|
|
SEQCNT = 0x0000_2064, // Sequencer Command Count Register
|
|
CMDFIFOWRITE = 0x0000_2070, // Command FIFO Write Register
|
|
TEMPSENSDAT = 0x0000_2084, // Temperature Sensor Result Register
|
|
ADCDAT = 0x0000_2074, // ADC Raw Result Register
|
|
LPTIASW0 = 0x0000_20E4, // Low power TIA switch configuration
|
|
LPTIACON0 = 0x0000_20EC, // Low power TIA control bits, Channel 0
|
|
LPDACDAT0 = 0x0000_2120, // Low power DAC data output Register
|
|
LPDACCON0 = 0x0000_2128, // Low power DAC configuration register
|
|
TEMPSENS = 0x0000_2174, // Temperature Sensor Configuration Register
|
|
ADCCON = 0x0000_21A8, // ADC Configuration Register
|
|
SEQ0INFO = 0x0000_21CC, // Sequence 0 Information Register
|
|
SEQ1INFO = 0x0000_21E8, // Sequence 1 Information Register
|
|
SEQ2INFO = 0x0000_21D0, // Sequence 2 Information Register
|
|
CMDDATACON = 0x0000_21D8, // Command Data Control Register
|
|
SEQ3INFO = 0x0000_21E4, // Sequence 3 Information Register
|
|
AFEGENINTSTA = 0x0000_209C, // Analog Generation Interrupt Register
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CMDFIFOWADDR = 0x0000_21D4, // Command FIFO Write Address Register
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PMBW = 0x0000_22F0, // Power Mode Configuration Register
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SWMUX = 0x0000_235C, // Common-mode switch mux select register
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INTCFLAG0 = 0x0000_3010, // Interrupt Control Flag 0 Register
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INTCFLAG1 = 0x0000_3014, // Interrupt Control Flag 1 Register
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OSCCON = 0x0000_0A10, // Oscillator Control Register
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SEQTIMEOUT = 0x0000_2068, // Sequencer Timeout Counter Register
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SEQCRC = 0x0000_2060, // Sequencer CRC Value Register
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DFTREAL = 0x0000_2078, // DFT Result, Real Device Register
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DFTIMAG = 0x0000_207C, // DFT Result, Imaginary Device Register
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DATAFIFOTHRES = 0x0000_21E0, // Data FIFO Threshold Register
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SYNCEXTDEVICE = 0x0000_2054, // Sync External Device Register
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GP0CON = 0x0000_0000, // GPIO Port 0 Configuration Register
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DATAFIFORD = 0x0000_206C, // Data FIFO Read Register
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DFTCON = 0x0000_20D0, // DFT Configuration Register
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HSDACCON = 0x0000_2010, // High Speed DAC Configuration Register
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HSRTIACON = 0x0000_20F0, // High Speed RTIA Configuration Register
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BUFSENCON = 0x0000_2180, // HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER
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FIFOCNTSTA = 0x0000_2200, // Command and data FIFO internal data count register
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ADCFILTERCON = 0x0000_2044, // ADC Output Filters Configuration Register
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CLKCON0 = 0x0000_0408, // Clock Divider Configuration Register
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HSOSCCON = 0x0000_20BC, // High Power Oscillator Configuration Register
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} |