LUMZ-bioz/bioz-firmware-rs
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Implemented registers in lib.

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Hubald Verzijl
2025-07-28 17:17:37 +02:00
parent e6c3d6d06f
commit f0e9fbc52c
2 changed files with 92 additions and 26 deletions
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113
src/ad5940.rs
View File

@@ -127,6 +127,77 @@ impl AD5940 {
Ok(()) Ok(())
} }
pub async fn afecon(&mut self, ctr: ConfigurationRegister, state: bool) {
let reg = self.read_reg_32(Register::AFECON).await.unwrap();
let mut reg = ConfigurationRegister::from_bits_truncate(reg);
let flags = [
ConfigurationRegister::DACBUFEN,
ConfigurationRegister::DACREFEN,
ConfigurationRegister::SINC2EN,
ConfigurationRegister::DFTEN,
ConfigurationRegister::WAVEGENEN,
ConfigurationRegister::TEMPCONVEN,
ConfigurationRegister::TEMPSENSEN,
ConfigurationRegister::TIAEN,
ConfigurationRegister::INAMPEN,
ConfigurationRegister::EXBUFEN,
ConfigurationRegister::ADCCONVEN,
ConfigurationRegister::ADCEN,
ConfigurationRegister::DACEN,
ConfigurationRegister::HSREFDIS,
];
for &flag in flags.iter() {
if ctr.contains(flag) {
reg = if state {
reg | flag
} else {
reg & !flag
};
}
}
self.write_reg_32(Register::AFECON, reg.bits()).await.unwrap();
}
pub async fn swcon(&mut self, ctr: SwitchMatrixConfigurationRegister) {
let reg = self.read_reg_32(Register::SWCON).await.unwrap();
let mut reg = SwitchMatrixConfigurationRegister::from_bits_truncate(reg);
// NMUXCON
if (ctr & SwitchMatrixConfigurationRegister::NMUXCON_MSK) == SwitchMatrixConfigurationRegister::NMUXCON_N2 {
reg &= !SwitchMatrixConfigurationRegister::NMUXCON_MSK;
reg |= SwitchMatrixConfigurationRegister::NMUXCON_N2;
} else if (ctr & SwitchMatrixConfigurationRegister::NMUXCON_MSK) == SwitchMatrixConfigurationRegister::NMUXCON_N5 {
reg &= !SwitchMatrixConfigurationRegister::NMUXCON_MSK;
reg |= SwitchMatrixConfigurationRegister::NMUXCON_N5;
};
// PMUXCON
if (ctr & SwitchMatrixConfigurationRegister::PMUXCON_MSK) == SwitchMatrixConfigurationRegister::PMUXCON_P2 {
reg &= !SwitchMatrixConfigurationRegister::PMUXCON_MSK;
reg |= SwitchMatrixConfigurationRegister::PMUXCON_P2;
} else if (ctr & SwitchMatrixConfigurationRegister::PMUXCON_MSK) == SwitchMatrixConfigurationRegister::PMUXCON_P11 {
reg &= !SwitchMatrixConfigurationRegister::PMUXCON_MSK;
reg |= SwitchMatrixConfigurationRegister::PMUXCON_P11;
}
// DMUXCON
if ctr.contains(SwitchMatrixConfigurationRegister::DMUXCON_D5) {
reg &= !SwitchMatrixConfigurationRegister::DMUXCON_MSK;
reg |= SwitchMatrixConfigurationRegister::DMUXCON_D5;
}
self.write_reg_32(Register::SWCON, reg.bits()).await.unwrap();
}
pub async fn wgfcw(&mut self, frequency: u32) {
let sinefcw = (frequency as f64) * (1_073_741_824.0 / 16_000_000.0);
let sinefcw = 0x00FFFFFF & sinefcw as u32;
self.write_reg_32(Register::WGFCW, sinefcw).await.unwrap();
}
pub async fn get_chipid(&mut self) -> Result<u16, Error> { pub async fn get_chipid(&mut self) -> Result<u16, Error> {
self.read_reg_16(Register::CHIPID).await self.read_reg_16(Register::CHIPID).await
} }
@@ -137,17 +208,14 @@ impl AD5940 {
pub async fn init_temperature(&mut self) -> Result<(), Error> { pub async fn init_temperature(&mut self) -> Result<(), Error> {
// AFECON: // AFECON:
let mut config_afecon = ConfigurationRegister::reset.bits() | ConfigurationRegister::TEMPSENSEN.bits() | ConfigurationRegister::ADCEN.bits(); self.afecon(ConfigurationRegister::TEMPSENSEN | ConfigurationRegister::ADCEN, true).await;
self.write_reg_32(Register::AFECON, config_afecon).await?;
// ADCCON // ADCCON
let config_adccon = ADCConfigurationRegister::GNPGA_1_5.bits() | ADCConfigurationRegister::MUXSELN_TEMP.bits() | ADCConfigurationRegister::MUXSELP_TEMP.bits(); let config_adccon = ADCConfigurationRegister::GNPGA_1_5.bits() | ADCConfigurationRegister::MUXSELN_TEMP.bits() | ADCConfigurationRegister::MUXSELP_TEMP.bits();
self.write_reg_32(Register::ADCCON, config_adccon).await?; self.write_reg_32(Register::ADCCON, config_adccon).await?;
// AFECON - start conversion // AFECON - start conversion
config_afecon |= ConfigurationRegister::TEMPCONVEN.bits(); self.afecon(ConfigurationRegister::TEMPCONVEN | ConfigurationRegister::ADCCONVEN, true).await;
config_afecon |= ConfigurationRegister::ADCCONVEN.bits();
self.write_reg_32(Register::AFECON, config_afecon).await?;
Ok(()) Ok(())
} }
@@ -165,13 +233,11 @@ impl AD5940 {
pub async fn init_waveform(&mut self) -> Result<(), Error> { pub async fn init_waveform(&mut self) -> Result<(), Error> {
// Set frequency // Set frequency
let freq: u32 = 2000; let freq: u32 = 1000;
let sinefcw = (freq as f64) * (1_073_741_824.0 / 16_000_000.0); self.wgfcw(freq).await;
let sinefcw = 0x00FFFFFF & sinefcw as u32;
self.write_reg_32(Register::WGFCW, sinefcw).await?;
// Init amplitude // Init amplitude
let wg_amplitude = 1279; let wg_amplitude = 2047; // 2047 is the maximum amplitude for a 12-bit DAC --> 1.62V peak-to-peak
self.write_reg_32(Register::WGAMPLITUDE, wg_amplitude).await?; self.write_reg_32(Register::WGAMPLITUDE, wg_amplitude).await?;
// WGCON, enable waveform generator and set to sinusoidal, NO DACCAL // WGCON, enable waveform generator and set to sinusoidal, NO DACCAL
@@ -179,22 +245,21 @@ impl AD5940 {
self.write_reg_32(Register::WGCON, config_wgcon).await?; self.write_reg_32(Register::WGCON, config_wgcon).await?;
// SWCON - set up switch matrix // SWCON - set up switch matrix
let mut swcon = SwitchMatrixConfigurationRegister::reset.bits(); self.swcon(
SwitchMatrixConfigurationRegister::NMUXCON_N2
swcon &= !SwitchMatrixConfigurationRegister::NMUXCON_MSK.bits(); | SwitchMatrixConfigurationRegister::PMUXCON_P11
swcon |= SwitchMatrixConfigurationRegister::NMUXCON_N2.bits(); | SwitchMatrixConfigurationRegister::DMUXCON_D5).await;
swcon &= !SwitchMatrixConfigurationRegister::PMUXCON_MSK.bits();
swcon |= SwitchMatrixConfigurationRegister::PMUXCON_P11.bits();
swcon &= !SwitchMatrixConfigurationRegister::DMUXCON_MSK.bits();
swcon |= SwitchMatrixConfigurationRegister::DMUXCON_D5.bits();
self.write_reg_32(Register::SWCON, swcon).await?;
// AFECON: // AFECON:
let config_afecon = ConfigurationRegister::reset.bits() | ConfigurationRegister::DACREFEN.bits() | ConfigurationRegister::EXBUFEN.bits() | ConfigurationRegister::INAMPEN.bits() | ConfigurationRegister::DACEN.bits() | ConfigurationRegister::WAVEGENEN.bits(); self.afecon(
self.write_reg_32(Register::AFECON, config_afecon).await?; ConfigurationRegister::DACREFEN
| ConfigurationRegister::EXBUFEN
| ConfigurationRegister::INAMPEN
| ConfigurationRegister::DACEN
| ConfigurationRegister::WAVEGENEN,
true,
)
.await;
Ok(()) Ok(())
} }

5
src/ad5940_registers.rs
View File

@@ -2,8 +2,8 @@ use bitflags::bitflags;
bitflags! { bitflags! {
// Address 0x00002000, Reset: 0x00080000, Name: AFECON // Address 0x00002000, Reset: 0x00080000, Name: AFECON
#[derive(Clone, Copy)]
pub struct ConfigurationRegister: u32 { pub struct ConfigurationRegister: u32 {
const reset = 0x00080000;
const DACBUFEN = 1 << 21; const DACBUFEN = 1 << 21;
const DACREFEN = 1 << 20; const DACREFEN = 1 << 20;
const SINC2EN = 1 << 16; const SINC2EN = 1 << 16;
@@ -23,8 +23,9 @@ bitflags! {
bitflags! { bitflags! {
// Address 0x0000200C, Reset: 0x00000000, Name: SWCON // Address 0x0000200C, Reset: 0x00000000, Name: SWCON
#[derive(Clone, Copy)]
#[derive(PartialEq)]
pub struct SwitchMatrixConfigurationRegister: u32 { pub struct SwitchMatrixConfigurationRegister: u32 {
const reset = 0x0000_FFFF;
const NMUXCON_MSK = 0b1111 << 8; const NMUXCON_MSK = 0b1111 << 8;
const NMUXCON_N2 = 0b0010 << 8; // N2 switch const NMUXCON_N2 = 0b0010 << 8; // N2 switch
const NMUXCON_N5 = 0b0101 << 8; // N5 switch const NMUXCON_N5 = 0b0101 << 8; // N5 switch