From d04f457c9f19b85a0a78aeb2208dd5ca835c9a93 Mon Sep 17 00:00:00 2001 From: Hubald Verzijl Date: Wed, 30 Jul 2025 12:04:46 +0200 Subject: [PATCH] Update register names --- src/ad5940.rs | 90 ++++++++++++++++++++--------------------- src/ad5940_registers.rs | 12 ++++-- 2 files changed, 53 insertions(+), 49 deletions(-) diff --git a/src/ad5940.rs b/src/ad5940.rs index 6dbab8f..c024e58 100644 --- a/src/ad5940.rs +++ b/src/ad5940.rs @@ -127,25 +127,25 @@ impl AD5940 { Ok(()) } - pub async fn afecon(&mut self, ctr: ConfigurationRegister, state: bool) { + pub async fn afecon(&mut self, ctr: AFECON, state: bool) { let reg = self.read_reg_32(Register::AFECON).await.unwrap(); - let mut reg = ConfigurationRegister::from_bits_truncate(reg); + let mut reg = AFECON::from_bits_truncate(reg); let flags = [ - ConfigurationRegister::DACBUFEN, - ConfigurationRegister::DACREFEN, - ConfigurationRegister::SINC2EN, - ConfigurationRegister::DFTEN, - ConfigurationRegister::WAVEGENEN, - ConfigurationRegister::TEMPCONVEN, - ConfigurationRegister::TEMPSENSEN, - ConfigurationRegister::TIAEN, - ConfigurationRegister::INAMPEN, - ConfigurationRegister::EXBUFEN, - ConfigurationRegister::ADCCONVEN, - ConfigurationRegister::ADCEN, - ConfigurationRegister::DACEN, - ConfigurationRegister::HSREFDIS, + AFECON::DACBUFEN, + AFECON::DACREFEN, + AFECON::SINC2EN, + AFECON::DFTEN, + AFECON::WAVEGENEN, + AFECON::TEMPCONVEN, + AFECON::TEMPSENSEN, + AFECON::TIAEN, + AFECON::INAMPEN, + AFECON::EXBUFEN, + AFECON::ADCCONVEN, + AFECON::ADCEN, + AFECON::DACEN, + AFECON::HSREFDIS, ]; for &flag in flags.iter() { @@ -161,32 +161,32 @@ impl AD5940 { self.write_reg_32(Register::AFECON, reg.bits()).await.unwrap(); } - pub async fn swcon(&mut self, ctr: SwitchMatrixConfigurationRegister) { + pub async fn swcon(&mut self, ctr: SWCON) { let reg = self.read_reg_32(Register::SWCON).await.unwrap(); - let mut reg = SwitchMatrixConfigurationRegister::from_bits_truncate(reg); + let mut reg = SWCON::from_bits_truncate(reg); // NMUXCON - if (ctr & SwitchMatrixConfigurationRegister::NMUXCON_MSK) == SwitchMatrixConfigurationRegister::NMUXCON_N2 { - reg &= !SwitchMatrixConfigurationRegister::NMUXCON_MSK; - reg |= SwitchMatrixConfigurationRegister::NMUXCON_N2; - } else if (ctr & SwitchMatrixConfigurationRegister::NMUXCON_MSK) == SwitchMatrixConfigurationRegister::NMUXCON_N5 { - reg &= !SwitchMatrixConfigurationRegister::NMUXCON_MSK; - reg |= SwitchMatrixConfigurationRegister::NMUXCON_N5; + if (ctr & SWCON::NMUXCON_MSK) == SWCON::NMUXCON_N2 { + reg &= !SWCON::NMUXCON_MSK; + reg |= SWCON::NMUXCON_N2; + } else if (ctr & SWCON::NMUXCON_MSK) == SWCON::NMUXCON_N5 { + reg &= !SWCON::NMUXCON_MSK; + reg |= SWCON::NMUXCON_N5; }; // PMUXCON - if (ctr & SwitchMatrixConfigurationRegister::PMUXCON_MSK) == SwitchMatrixConfigurationRegister::PMUXCON_P2 { - reg &= !SwitchMatrixConfigurationRegister::PMUXCON_MSK; - reg |= SwitchMatrixConfigurationRegister::PMUXCON_P2; - } else if (ctr & SwitchMatrixConfigurationRegister::PMUXCON_MSK) == SwitchMatrixConfigurationRegister::PMUXCON_P11 { - reg &= !SwitchMatrixConfigurationRegister::PMUXCON_MSK; - reg |= SwitchMatrixConfigurationRegister::PMUXCON_P11; + if (ctr & SWCON::PMUXCON_MSK) == SWCON::PMUXCON_P2 { + reg &= !SWCON::PMUXCON_MSK; + reg |= SWCON::PMUXCON_P2; + } else if (ctr & SWCON::PMUXCON_MSK) == SWCON::PMUXCON_P11 { + reg &= !SWCON::PMUXCON_MSK; + reg |= SWCON::PMUXCON_P11; } // DMUXCON - if ctr.contains(SwitchMatrixConfigurationRegister::DMUXCON_D5) { - reg &= !SwitchMatrixConfigurationRegister::DMUXCON_MSK; - reg |= SwitchMatrixConfigurationRegister::DMUXCON_D5; + if ctr.contains(SWCON::DMUXCON_D5) { + reg &= !SWCON::DMUXCON_MSK; + reg |= SWCON::DMUXCON_D5; } self.write_reg_32(Register::SWCON, reg.bits()).await.unwrap(); @@ -208,14 +208,14 @@ impl AD5940 { pub async fn init_temperature(&mut self) -> Result<(), Error> { // AFECON: - self.afecon(ConfigurationRegister::TEMPSENSEN | ConfigurationRegister::ADCEN, true).await; + self.afecon(AFECON::TEMPSENSEN | AFECON::ADCEN, true).await; // ADCCON - let config_adccon = ADCConfigurationRegister::GNPGA_1_5.bits() | ADCConfigurationRegister::MUXSELN_TEMP.bits() | ADCConfigurationRegister::MUXSELP_TEMP.bits(); + let config_adccon = ADCCON::GNPGA_1_5.bits() | ADCCON::MUXSELN_TEMP.bits() | ADCCON::MUXSELP_TEMP.bits(); self.write_reg_32(Register::ADCCON, config_adccon).await?; // AFECON - start conversion - self.afecon(ConfigurationRegister::TEMPCONVEN | ConfigurationRegister::ADCCONVEN, true).await; + self.afecon(AFECON::TEMPCONVEN | AFECON::ADCCONVEN, true).await; Ok(()) } @@ -241,22 +241,22 @@ impl AD5940 { self.write_reg_32(Register::WGAMPLITUDE, wg_amplitude).await?; // WGCON, enable waveform generator and set to sinusoidal, NO DACCAL - let config_wgcon = WaveformGeneratorConfigurationRegister::TYPESEL_SIN.bits(); + let config_wgcon = WGCON::TYPESEL_SIN.bits(); self.write_reg_32(Register::WGCON, config_wgcon).await?; // SWCON - set up switch matrix self.swcon( - SwitchMatrixConfigurationRegister::NMUXCON_N2 - | SwitchMatrixConfigurationRegister::PMUXCON_P11 - | SwitchMatrixConfigurationRegister::DMUXCON_D5).await; + SWCON::NMUXCON_N2 + | SWCON::PMUXCON_P11 + | SWCON::DMUXCON_D5).await; // AFECON: self.afecon( - ConfigurationRegister::DACREFEN - | ConfigurationRegister::EXBUFEN - | ConfigurationRegister::INAMPEN - | ConfigurationRegister::DACEN - | ConfigurationRegister::WAVEGENEN, + AFECON::DACREFEN + | AFECON::EXBUFEN + | AFECON::INAMPEN + | AFECON::DACEN + | AFECON::WAVEGENEN, true, ) .await; diff --git a/src/ad5940_registers.rs b/src/ad5940_registers.rs index 64fc7dc..ea269c5 100644 --- a/src/ad5940_registers.rs +++ b/src/ad5940_registers.rs @@ -1,9 +1,10 @@ use bitflags::bitflags; bitflags! { + // Configuration Register // Address 0x00002000, Reset: 0x00080000, Name: AFECON #[derive(Clone, Copy)] - pub struct ConfigurationRegister: u32 { + pub struct AFECON: u32 { const DACBUFEN = 1 << 21; const DACREFEN = 1 << 20; const SINC2EN = 1 << 16; @@ -22,10 +23,11 @@ bitflags! { } bitflags! { + // Switch Matrix Configuration Register // Address 0x0000200C, Reset: 0x00000000, Name: SWCON #[derive(Clone, Copy)] #[derive(PartialEq)] - pub struct SwitchMatrixConfigurationRegister: u32 { + pub struct SWCON: u32 { const NMUXCON_MSK = 0b1111 << 8; const NMUXCON_N2 = 0b0010 << 8; // N2 switch const NMUXCON_N5 = 0b0101 << 8; // N5 switch @@ -38,8 +40,9 @@ bitflags! { } bitflags! { + // Waveform Generator Configuration Register // Address 0x00002014, Reset: 0x00000030, Name: WGCON - pub struct WaveformGeneratorConfigurationRegister: u32 { + pub struct WGCON: u32 { const reset = 0x00000030; const DACGAINCAL = 1 << 5; const DACOFFSETCAL = 1 << 4; @@ -51,8 +54,9 @@ bitflags! { } bitflags! { + // ADC Configuration Register, // Address 0x000021A8, Reset: 0x00000000, Name: ADCCON - pub struct ADCConfigurationRegister: u32 { + pub struct ADCCON: u32 { const GNPGA_1_5 = 1 << 16; const MUXSELN_TEMP = 0b01011 << 8; const MUXSELP_TEMP = 0b01011;