Minor improvements

This commit is contained in:
2025-08-28 11:33:33 +02:00
parent 044cfb069a
commit 83731f77e0
2 changed files with 3 additions and 8 deletions

View File

@@ -47,7 +47,7 @@ impl ImpedanceSetup {
.adc_mux_n(MUXSELN::HsTiaNeg) .adc_mux_n(MUXSELN::HsTiaNeg)
.adc_mux_p(MUXSELP::HsTiaPos) .adc_mux_p(MUXSELP::HsTiaPos)
.ctiacon(CTIACON::C32) .ctiacon(CTIACON::C32)
.rtiacon(RTIACON::R5k) .rtiacon(RTIACON::R1k)
.sinc3osr(SINC3OSR::R5) .sinc3osr(SINC3OSR::R5)
.sinc2osr(SINC2OSR::R178) .sinc2osr(SINC2OSR::R178)
.adcsamplerate(ADCSAMPLERATE::R800kHz) .adcsamplerate(ADCSAMPLERATE::R800kHz)
@@ -92,7 +92,7 @@ impl ImpedanceSetup {
self.ad5940.sequencer_enable(true).await; self.ad5940.sequencer_enable(true).await;
self.ad5940.wgfcw(frequency).await; self.ad5940.wgfcw(frequency).await;
let wg_amplitude = 557; // 2047 is the maximum amplitude for a 12-bit DAC --> 1.62V peak-to-peak let wg_amplitude = 2047; // 2047 is the maximum amplitude for a 12-bit DAC --> 1.62V peak-to-peak
self.ad5940.write_reg(Register::WGAMPLITUDE, wg_amplitude).await.unwrap(); self.ad5940.write_reg(Register::WGAMPLITUDE, wg_amplitude).await.unwrap();
// Rcal // Rcal

View File

@@ -230,12 +230,7 @@ const RCAL_VAL: f32 = 1000.0;
/// Convert raw 18-bit 2's complement value to signed i32 /// Convert raw 18-bit 2's complement value to signed i32
fn sign_extend_18bit(val: u32) -> i32 { fn sign_extend_18bit(val: u32) -> i32 {
let masked = val & 0x3FFFF; ((val << 14) as i32) >> 14
if masked & (1 << 17) != 0 {
(masked | 0xFFFC0000) as i32
} else {
masked as i32
}
} }
/// Calculate magnitude and phase of Rz using Rcal reference /// Calculate magnitude and phase of Rz using Rcal reference