Included setting dft number from gui.

This commit is contained in:
2025-09-12 22:42:23 +02:00
parent b53e58ec31
commit 230602f7c8
5 changed files with 60 additions and 22 deletions

View File

@@ -87,57 +87,57 @@ pub struct DspConfig {
} }
impl DspConfig { impl DspConfig {
pub fn adc_mux_n(mut self, muxseln: MUXSELN) -> Self { pub fn adc_mux_n(&mut self, muxseln: MUXSELN) -> &mut Self {
self.muxseln = Some(muxseln); self.muxseln = Some(muxseln);
self self
} }
pub fn adc_mux_p(mut self, muxselp: MUXSELP) -> Self { pub fn adc_mux_p(&mut self, muxselp: MUXSELP) -> &mut Self {
self.muxselp = Some(muxselp); self.muxselp = Some(muxselp);
self self
} }
pub fn ctiacon(mut self, ctiacon: CTIACON) -> Self { pub fn ctiacon(&mut self, ctiacon: CTIACON) -> &mut Self {
self.ctiacon = Some(ctiacon); self.ctiacon = Some(ctiacon);
self self
} }
pub fn rtiacon(mut self, rtiacon: RTIACON) -> Self { pub fn rtiacon(&mut self, rtiacon: RTIACON) -> &mut Self {
self.rtiacon = Some(rtiacon); self.rtiacon = Some(rtiacon);
self self
} }
pub fn sinc3osr(mut self, sinc3osr: SINC3OSR) -> Self { pub fn sinc3osr(&mut self, sinc3osr: SINC3OSR) -> &mut Self {
self.sinc3osr = Some(sinc3osr); self.sinc3osr = Some(sinc3osr);
self self
} }
pub fn sinc2osr(mut self, sinc2osr: SINC2OSR) -> Self { pub fn sinc2osr(&mut self, sinc2osr: SINC2OSR) -> &mut Self {
self.sinc2osr = Some(sinc2osr); self.sinc2osr = Some(sinc2osr);
self self
} }
pub fn adcsamplerate(mut self, adcsamplerate: ADCSAMPLERATE) -> Self { pub fn adcsamplerate(&mut self, adcsamplerate: ADCSAMPLERATE) -> &mut Self {
self.adcsamplerate = Some(adcsamplerate); self.adcsamplerate = Some(adcsamplerate);
self self
} }
pub fn dftin_sel(mut self, dftin: DFTINSEL) -> Self { pub fn dftin_sel(&mut self, dftin: DFTINSEL) -> &mut Self {
self.dftin = Some(dftin); self.dftin = Some(dftin);
self self
} }
pub fn dftnum(mut self, dftnum: DFTNUM) -> Self { pub fn dftnum(&mut self, dftnum: DFTNUM) -> &mut Self {
self.dftnum = Some(dftnum); self.dftnum = Some(dftnum);
self self
} }
pub fn hanning(mut self, hanning: bool) -> Self { pub fn hanning(&mut self, hanning: bool) -> &mut Self {
self.hanning = Some(hanning); self.hanning = Some(hanning);
self self
} }
pub fn set_clks(mut self, fsys: u32, fadc: u32) -> Self { pub fn set_clks(&mut self, fsys: u32, fadc: u32) -> &mut Self {
self.fsys = Some(fsys); self.fsys = Some(fsys);
self.fadc = Some(fadc); self.fadc = Some(fadc);
self.ratio_sys2adc_clk = Some(fsys as f32 / fadc as f32); self.ratio_sys2adc_clk = Some(fsys as f32 / fadc as f32);
@@ -156,27 +156,27 @@ pub struct SramConfig {
} }
impl SramConfig { impl SramConfig {
pub fn datafifosrcsel(mut self, datafifosrcsel: DATAFIFOSRCSEL) -> Self { pub fn datafifosrcsel(&mut self, datafifosrcsel: DATAFIFOSRCSEL) -> &mut Self {
self.datafifosrcsel = Some(datafifosrcsel); self.datafifosrcsel = Some(datafifosrcsel);
self self
} }
pub fn datafifoen(mut self, datafifoen: DATAFIFOEN) -> Self { pub fn datafifoen(&mut self, datafifoen: DATAFIFOEN) -> &mut Self {
self.datafifoen = Some(datafifoen); self.datafifoen = Some(datafifoen);
self self
} }
pub fn data_size(mut self, data_mem_size: DATA_MEM_SEL) -> Self { pub fn data_size(&mut self, data_mem_size: DATA_MEM_SEL) -> &mut Self {
self.data_mem_size = Some(data_mem_size); self.data_mem_size = Some(data_mem_size);
self self
} }
pub fn cmd_mode(mut self, cmd_mem_mode: CMDMEMMDE) -> Self { pub fn cmd_mode(&mut self, cmd_mem_mode: CMDMEMMDE) -> &mut Self {
self.cmd_mem_mode = Some(cmd_mem_mode); self.cmd_mem_mode = Some(cmd_mem_mode);
self self
} }
pub fn cmd_size(mut self, cmd_mem_size: CMD_MEM_SEL) -> Self { pub fn cmd_size(&mut self, cmd_mem_size: CMD_MEM_SEL) -> &mut Self {
self.cmd_mem_size = Some(cmd_mem_size); self.cmd_mem_size = Some(cmd_mem_size);
self self
} }

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@@ -169,7 +169,7 @@ pub async fn start_single_impedance_handler(context: SpawnCtx, header: VarHeader
context.impedance_setup.lock().await.running = true; context.impedance_setup.lock().await.running = true;
// Init the sequencer // Init the sequencer
context.impedance_setup.lock().await.init_single_frequency_measurement(rqst.sinus_frequency).await; context.impedance_setup.lock().await.init_single_frequency_measurement(rqst.sinus_frequency, rqst.dft_number).await;
// Trigger the sequencer // Trigger the sequencer
context.impedance_setup.lock().await.start_measurement().await; context.impedance_setup.lock().await.start_measurement().await;

27
src/icd_mapping.rs Normal file
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@@ -0,0 +1,27 @@
use crate::ad5940_registers::DFTNUM;
use bioz_icd_rs::IcdDftNum;
// Map ICD types to register types
pub trait IntoDftnum {
fn into_dftnum(self) -> DFTNUM;
}
impl IntoDftnum for IcdDftNum {
fn into_dftnum(self) -> DFTNUM {
match self {
IcdDftNum::Num4 => DFTNUM::Num4,
IcdDftNum::Num8 => DFTNUM::Num8,
IcdDftNum::Num16 => DFTNUM::Num16,
IcdDftNum::Num32 => DFTNUM::Num32,
IcdDftNum::Num64 => DFTNUM::Num64,
IcdDftNum::Num128 => DFTNUM::Num128,
IcdDftNum::Num256 => DFTNUM::Num256,
IcdDftNum::Num512 => DFTNUM::Num512,
IcdDftNum::Num1024 => DFTNUM::Num1024,
IcdDftNum::Num2048 => DFTNUM::Num2048,
IcdDftNum::Num4096 => DFTNUM::Num4096,
IcdDftNum::Num8192 => DFTNUM::Num8192,
IcdDftNum::Num16384 => DFTNUM::Num16384,
}
}
}

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@@ -10,7 +10,8 @@ use static_cell::StaticCell;
use crate::ad5940::*; use crate::ad5940::*;
use crate::ad5940_registers::*; use crate::ad5940_registers::*;
use bioz_icd_rs::ImpedanceOutput; use bioz_icd_rs::{ImpedanceOutput, IcdDftNum};
use crate::icd_mapping::IntoDftnum;
pub static IMPEDANCE_CHANNEL: Channel<ThreadModeRawMutex, ImpedanceOutput, 2000> = Channel::new(); pub static IMPEDANCE_CHANNEL: Channel<ThreadModeRawMutex, ImpedanceOutput, 2000> = Channel::new();
@@ -51,7 +52,8 @@ impl ImpedanceSetup {
self.ad5940.apply_clk_config(&clk_config).await.unwrap(); self.ad5940.apply_clk_config(&clk_config).await.unwrap();
// Set DSP configuration // Set DSP configuration
let dsp_config = DspConfig::default() let mut dsp_config = DspConfig::default();
dsp_config
.adc_mux_n(MUXSELN::HsTiaNeg) .adc_mux_n(MUXSELN::HsTiaNeg)
.adc_mux_p(MUXSELP::HsTiaPos) .adc_mux_p(MUXSELP::HsTiaPos)
.ctiacon(CTIACON::C32) .ctiacon(CTIACON::C32)
@@ -68,7 +70,8 @@ impl ImpedanceSetup {
self.dsp_config = Some(dsp_config); self.dsp_config = Some(dsp_config);
// Set SRAM configuration (cmd and data sram) // Set SRAM configuration (cmd and data sram)
let sram_config = SramConfig::default() let mut sram_config = SramConfig::default();
sram_config
.datafifosrcsel(DATAFIFOSRCSEL::DFT) .datafifosrcsel(DATAFIFOSRCSEL::DFT)
.datafifoen(DATAFIFOEN::Normal) .datafifoen(DATAFIFOEN::Normal)
.data_size(DATA_MEM_SEL::Size2kB) .data_size(DATA_MEM_SEL::Size2kB)
@@ -83,7 +86,11 @@ impl ImpedanceSetup {
Ok(()) Ok(())
} }
pub async fn init_single_frequency_measurement(&mut self, frequency: u32) { pub async fn init_single_frequency_measurement(&mut self, frequency: u32, dft_number: IcdDftNum) {
// Set DFT number
self.dsp_config.as_mut().unwrap().dftnum(dft_number.into_dftnum());
self.ad5940.apply_dsp_config(self.dsp_config.as_ref().unwrap()).await.unwrap();
// Configure GPIOs // Configure GPIOs
self.ad5940.write_reg(Register::GP0CON, 0b10 << 4 | 0b10 << 2 | 0b10).await.unwrap(); self.ad5940.write_reg(Register::GP0CON, 0b10 << 4 | 0b10 << 2 | 0b10).await.unwrap();
self.ad5940.write_reg(Register::SYNCEXTDEVICE, 0b111).await.unwrap(); self.ad5940.write_reg(Register::SYNCEXTDEVICE, 0b111).await.unwrap();
@@ -150,6 +157,8 @@ impl ImpedanceSetup {
self.start_measurement().await; self.start_measurement().await;
} }
pub async fn start_measurement(&mut self) { pub async fn start_measurement(&mut self) {
self.ad5940.sequencer_trigger(0).await; self.ad5940.sequencer_trigger(0).await;
} }

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@@ -40,6 +40,8 @@ use impedance::IMPEDANCE_CHANNEL;
mod impedance; mod impedance;
use impedance::{ImpedanceSetup, ImpedanceSetupType, IMPEDANCE_SETUP}; use impedance::{ImpedanceSetup, ImpedanceSetupType, IMPEDANCE_SETUP};
mod icd_mapping;
bind_interrupts!(struct Irqs { bind_interrupts!(struct Irqs {
USB_DRD_FS => usb::InterruptHandler<peripherals::USB>; USB_DRD_FS => usb::InterruptHandler<peripherals::USB>;
}); });