bioz-firmware-rs/src/ad5940_registers.rs

use bitflags::bitflags;

#[allow(dead_code)]
pub trait RegisterField {
    /// Reset value for this field
    fn reset() -> Self;

    /// Bit offset of the field within the register
    const BIT_OFFSET: u32;

    /// Bitmask of the field (not shifted)
    const MASK: u32;

    /// Clears the field bits in the register
    fn clear(reg: u32) -> u32 {
        reg & !(Self::MASK << Self::BIT_OFFSET)
    }

    /// Applies a new value to the field in the register
    fn apply(reg: u32, val: u32) -> u32 {
        let cleared = reg & !(Self::MASK << Self::BIT_OFFSET);
        let shifted = (val & Self::MASK) << Self::BIT_OFFSET;
        cleared | shifted
    }
}

#[allow(dead_code)]
pub enum T9CON {
    T9Closed = 1,
    T9Open = 0,
}

impl RegisterField for T9CON {
    fn reset() -> Self {
        T9CON::T9Open
    }
    const BIT_OFFSET: u32 = 17;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
pub enum TMUXCON {
    AllOpen = 0b1111,
    T1Closed = 0b0001,
    T2Closed = 0b0010,
    T3Closed = 0b0011,
    T4Closed = 0b0100,
    T5Closed = 0b0101,
    T6Closed = 0b0110,
    T7Closed = 0b0111,
    TR1Closed = 0b1000,
    AllClosed = 0b1001,
}

impl RegisterField for TMUXCON {
    fn reset() -> Self {
        TMUXCON::AllOpen
    }
    const BIT_OFFSET: u32 = 12;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
pub enum NMUXCON {
    NLClosed = 0b0000,
    N1Closed = 0b0001,
    N2Closed = 0b0010,
    N3Closed = 0b0011,
    N4Closed = 0b0100,
    N5Closed = 0b0101,
    N6Closed = 0b0110,
    N7Closed = 0b0111,
    N9Closed = 0b1001,
    NR1Closed = 0b1010,
    NL1Closed = 0b1011,
    AllOpen = 0b1111,
}

impl RegisterField for NMUXCON {
    fn reset() -> Self {
        NMUXCON::AllOpen
    }
    const BIT_OFFSET: u32 = 8;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
pub enum PMUXCON {
    PLClosed = 0b0000,
    PR0Closed = 0b0001,
    P2Closed = 0b0010,
    P3Closed = 0b0011,
    P4Closed = 0b0100,
    P5Closed = 0b0101,
    P6Closed = 0b0110,
    P7Closed = 0b0111,
    P9Closed = 0b1001,
    P11Closed = 0b1011,
    PL2Closed = 0b1110,
    AllOpen = 0b1111,
}

impl RegisterField for PMUXCON {
    fn reset() -> Self {
        PMUXCON::AllOpen
    }
    const BIT_OFFSET: u32 = 4;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
pub enum DMUXCON {
    AllOpen = 0b1111,
    DR0Closed = 0b0001,
    D2Closed = 0b0010,
    D3Closed = 0b0011,
    D4Closed = 0b0100,
    D5Closed = 0b0101,
    D6Closed = 0b0110,
    D7Closed = 0b0111,
    P8Closed = 0b1000,
    AllClosed = 0b1001
}

impl RegisterField for DMUXCON {
    fn reset() -> Self {
        DMUXCON::AllOpen
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum RSTEN {
    Disabled = 0b0,
    Enabled  = 0b1,
}

impl RegisterField for RSTEN {
    fn reset() -> Self {
        RSTEN::Disabled
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum PWDEN {
    DACPoweredOn  = 0b0,
    DACPoweredOff = 0b1,
}

impl RegisterField for PWDEN {
    fn reset() -> Self {
        PWDEN::DACPoweredOff
    }
    const BIT_OFFSET: u32 = 1;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum DACIN6 {
    Default = 0b0,
}

impl RegisterField for DACIN6  {
    fn reset() -> Self {
        DACIN6::Default
    }
    const BIT_OFFSET: u32 = 12;
    const MASK: u32 = 0b11_1111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum SWMUX {
    CommonModeOff = 0b0,
    COmmonModeOn  = 0b1,
}

impl RegisterField for SWMUX {
    fn reset() -> Self {
        SWMUX::CommonModeOff
    }
    const BIT_OFFSET: u32 = 3;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum TIAPDEN {
    PowerUp = 0b0,
    PowerDown  = 0b1,
}

impl RegisterField for TIAPDEN {
    fn reset() -> Self {
        TIAPDEN::PowerDown
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum TIARF {
    Disconnected = 0b0,
    R0           = 0b1,
    R20k         = 0b10,
    R100k        = 0b11,
    R200k        = 0b100,
    R400k        = 0b101,
    R600k        = 0b110,
    R1M          = 0b111,
}

impl RegisterField for TIARF {
    fn reset() -> Self {
        TIARF::Disconnected
    }
    const BIT_OFFSET: u32 = 13;
    const MASK: u32 = 0b111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum GNPGAIN {
    Gain1   = 0b0,
    Gain1_5 = 0b1,
    Gain2   = 0b10,
    Gain4   = 0b11,
    Gain9   = 0b100,
}

impl RegisterField for GNPGAIN {
    fn reset() -> Self {
        GNPGAIN::Gain1
    }
    const BIT_OFFSET: u32 = 16;
    const MASK: u32 = 0b111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum MUXSELN 
{
    Floating = 0b00000,
    HsTiaNeg = 0b00001,
    LpTiaNeg = 0b00010,
    AIN1     = 0b00101,
    AIN2     = 0b00110,
    AIN3     = 0b00111,
    VBIAS_CAP= 0b01000,
    ExciNNode= 0b10100,
}

impl RegisterField for MUXSELN {
    fn reset() -> Self {
        MUXSELN::Floating
    }
    const BIT_OFFSET: u32 = 8;
    const MASK: u32 = 0b11111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum MUXSELP {
    Floating = 0b00000,
    HsTiaPos = 0b00001,
    AIN1     = 0b00101,
    AIN2     = 0b00110,
    AIN3     = 0b00111,
    CE0      = 0b011001,
    ExciPNode= 0b100100,
}

impl RegisterField for MUXSELP {
    fn reset() -> Self {
        MUXSELP::Floating
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b111111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum DFTINSEL {
    Sinc2       = 0b00,
    GainOffset  = 0b01,
    AdcRaw      = 0b10
}

impl RegisterField for DFTINSEL {
    fn reset() -> Self {
        DFTINSEL::Sinc2
    }
    const BIT_OFFSET: u32 = 20;
    const MASK: u32 = 0b11;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum DFTNUM {
    Num4       = 0b0000,
    Num8       = 0b0001,
    Num16      = 0b0010,
    Num32      = 0b0011,
    Num64      = 0b0100,
    Num128     = 0b0101,
    Num256     = 0b0110,
    Num512     = 0b0111,
    Num1024    = 0b1000,
    Num2048    = 0b1001,
    Num4096    = 0b1010,
    Num8192    = 0b1011,
    Num16384   = 0b1100,
}

impl RegisterField for DFTNUM {
    fn reset() -> Self {
        DFTNUM::Num2048
    }
    const BIT_OFFSET: u32 = 4;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum HANNING {
    Disable = 0,
    Enable = 1,
}

impl RegisterField for HANNING {
    fn reset() -> Self {
        HANNING::Disable
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum CTIACON {
    C1 = 0,
    C2 = 1 << 0,
    C4 = 1 << 1,
    C8 = 1 << 2,
    C16 = 1 << 3,
    C32 = 1 << 4,
}

impl RegisterField for CTIACON {
    fn reset() -> Self {
        CTIACON::C1
    }
    const BIT_OFFSET: u32 = 5;
    const MASK: u32 = 0b111_1111;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum RTIACON {
    R200 = 0b0000,
    R1k  = 0b0001,
    R5k  = 0b0010,
    R10k = 0b0011,
    R20k = 0b0100,
    R40k = 0b0101,
    R80k = 0b0110,
    R160k = 0b0111,
    Open = 0b1111,
}

impl RegisterField for RTIACON {
    fn reset() -> Self {
        RTIACON::Open
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum AVRGNUM {
    ADC2 = 0b00,
    ADC4 = 0b01,
    ADC8 = 0b10,
    ADC16 = 0b11,
}

impl RegisterField for AVRGNUM {
    fn reset() -> Self {
        AVRGNUM::ADC2
    }
    const BIT_OFFSET: u32 = 14;
    const MASK: u32 = 0b11;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum SINC3OSR {
    R5 = 0b00,
    R4 = 0b01,
    R2 = 0b10,
}

impl RegisterField for SINC3OSR {
    fn reset() -> Self {
        SINC3OSR::R5
    }
    const BIT_OFFSET: u32 = 12;
    const MASK: u32 = 0b11;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum SINC2OSR {
    R22 = 0b0000,
    R44 = 0b0001,
    R89 = 0b0010,
    R178 = 0b0011,
    R267 = 0b0100,
    R533 = 0b0101,
    R640 = 0b0110,
    R667 = 0b0111,
    R800 = 0b1000,
    R889 = 0b1001,
    R1067 = 0b1010,
    R1333 = 0b1011,
}

impl RegisterField for SINC2OSR {
    fn reset() -> Self {
        SINC2OSR::R178
    }
    const BIT_OFFSET: u32 = 8;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum AVRGEN {
    AverageDisabled = 0b0,
    AverageEnabled = 0b1,
}

impl RegisterField for AVRGEN {
    fn reset() -> Self {
        AVRGEN::AverageDisabled
    }
    const BIT_OFFSET: u32 = 7;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum ADCSAMPLERATE {
    R800kHz = 1,
    R1_6MHz = 0,
}

impl RegisterField for ADCSAMPLERATE {
    fn reset() -> Self {
        ADCSAMPLERATE::R1_6MHz
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum DATAMEMMDE {
    FIFOMode = 0b10,
    Stream = 0b11,
}

impl RegisterField for DATAMEMMDE {
    fn reset() -> Self {
        DATAMEMMDE::FIFOMode
    }
    const BIT_OFFSET: u32 = 9;
    const MASK: u32 = 0b11;
}

#[allow(dead_code, non_camel_case_types)]
#[derive(Copy, Clone)]
pub enum DATA_MEM_SEL {
    Reserved = 0b000,
    Size2kB = 0b001,
    Size4kB = 0b010,
    Size6kB = 0b011,
}

impl RegisterField for DATA_MEM_SEL {
    fn reset() -> Self {
        DATA_MEM_SEL::Reserved
    }
    const BIT_OFFSET: u32 = 6;
    const MASK: u32 = 0b111;
}

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum CMDMEMMDE {
    MemoryMode = 0b01,
    Reserved = 0b10,
}

impl RegisterField for CMDMEMMDE {
    fn reset() -> Self {
        CMDMEMMDE::Reserved
    }
    const BIT_OFFSET: u32 = 3;
    const MASK: u32 = 0b111;
}

#[allow(dead_code, non_camel_case_types)]
#[derive(Copy, Clone)]
pub enum CMD_MEM_SEL {
    Reserved = 0x0,
    Size2kB = 0x1,
    Size4kB = 0x2,
    Size6kB = 0x3,
}

impl RegisterField for CMD_MEM_SEL {
    fn reset() -> Self {
        CMD_MEM_SEL::Reserved
    }
    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b111;
}

#[allow(dead_code)]
#[derive(Clone, Copy)]
pub enum DATAFIFOSRCSEL {
    ADC = 0b000,
    DFT = 0b010,
    Sinc2 = 0b011,
    Variance = 0b100,
    Mean = 0b101,
}

impl RegisterField for DATAFIFOSRCSEL {
    fn reset() -> Self {
        DATAFIFOSRCSEL::ADC
    }
    const BIT_OFFSET: u32 = 13;
    const MASK: u32 = 0b111;
}

#[allow(dead_code)]
#[derive(Clone, Copy)]
pub enum DATAFIFOEN {
    FIFOisReset = 0b0,
    Normal = 0b1,
}

impl RegisterField for DATAFIFOEN {
    fn reset() -> Self {
        DATAFIFOEN::FIFOisReset
    }
    const BIT_OFFSET: u32 = 11;
    const MASK: u32 = 0b1;
}

#[allow(dead_code)]
#[derive(Clone, Copy)]
pub enum ADCCLKDIV {
    DIV1 = 0b01,
    DIV2 = 0b10,
}

impl RegisterField for ADCCLKDIV {
    fn reset() -> Self {
        Self::DIV1
    }
    const BIT_OFFSET: u32 = 6;
    const MASK: u32 = 0b1111;
}

#[allow(dead_code)]
#[derive(Clone, Copy)]
pub enum SYSCLKDIV {
    DIV1 = 1,
    DIV2,
    DIV3,
    DIV4,
    DIV5,
    DIV6,
    DIV7,
    DIV8,
    DIV9,
    DIV10,
    DIV11,
    DIV12,
    DIV13,
    DIV14,
    DIV15,
    DIV16,
    DIV17,
    DIV18,
    DIV19,
    DIV20,
    DIV21,
    DIV22,
    DIV23,
    DIV24,
    DIV25,
    DIV26,
    DIV27,
    DIV28,
    DIV29,
    DIV30,
    DIV31,
}

impl TryFrom<u8> for SYSCLKDIV {
    type Error = &'static str;

    fn try_from(value: u8) -> Result<Self, Self::Error> {
        match value {
            1 => Ok(SYSCLKDIV::DIV1),
            2 => Ok(SYSCLKDIV::DIV2),
            3 => Ok(SYSCLKDIV::DIV3),
            4 => Ok(SYSCLKDIV::DIV4),
            5 => Ok(SYSCLKDIV::DIV5),
            6 => Ok(SYSCLKDIV::DIV6),
            7 => Ok(SYSCLKDIV::DIV7),
            8 => Ok(SYSCLKDIV::DIV8),
            9 => Ok(SYSCLKDIV::DIV9),
            10 => Ok(SYSCLKDIV::DIV10),
            11 => Ok(SYSCLKDIV::DIV11),
            12 => Ok(SYSCLKDIV::DIV12),
            13 => Ok(SYSCLKDIV::DIV13),
            14 => Ok(SYSCLKDIV::DIV14),
            15 => Ok(SYSCLKDIV::DIV15),
            16 => Ok(SYSCLKDIV::DIV16),
            17 => Ok(SYSCLKDIV::DIV17),
            18 => Ok(SYSCLKDIV::DIV18),
            19 => Ok(SYSCLKDIV::DIV19),
            20 => Ok(SYSCLKDIV::DIV20),
            21 => Ok(SYSCLKDIV::DIV21),
            22 => Ok(SYSCLKDIV::DIV22),
            23 => Ok(SYSCLKDIV::DIV23),
            24 => Ok(SYSCLKDIV::DIV24),
            25 => Ok(SYSCLKDIV::DIV25),
            26 => Ok(SYSCLKDIV::DIV26),
            27 => Ok(SYSCLKDIV::DIV27),
            28 => Ok(SYSCLKDIV::DIV28),
            29 => Ok(SYSCLKDIV::DIV29),
            30 => Ok(SYSCLKDIV::DIV30),
            31 => Ok(SYSCLKDIV::DIV31),
            _ => Err("Invalid SYSCLKDIV value"),
        }
    }
}

impl SYSCLKDIV {
    pub fn div(value: u8) -> Self {
        SYSCLKDIV::try_from(value).unwrap_or(SYSCLKDIV::DIV1)
    }
}

impl RegisterField for SYSCLKDIV {
    fn reset() -> Self {
        SYSCLKDIV::DIV1
    }

    const BIT_OFFSET: u32 = 0;
    const MASK: u32 = 0b1_1111;
}

#[allow(dead_code)]
#[derive(Clone, Copy)]
pub enum CLK32MHZEN  {
    MHz32 = 0b0,
    Mhz16 = 0b1,
}

impl RegisterField for CLK32MHZEN {
    fn reset() -> Self {
        CLK32MHZEN::Mhz16
    }
    const BIT_OFFSET: u32 = 2;
    const MASK: u32 = 0b1;
}

bitflags! {
    // Configuration Register
    // Address 0x00002000, Reset: 0x00080000, Name: AFECON
    #[derive(Clone, Copy)]
    pub struct AFECON: u32 {
        const DACBUFEN = 1 << 21;
        const DACREFEN = 1 << 20;
        const SINC2EN = 1 << 16;
        const DFTEN = 1 << 15;
        const WAVEGENEN = 1 << 14;
        const TEMPCONVEN = 1 << 13;
        const TEMPSENSEN = 1 << 12;
        const TIAEN = 1 << 11;
        const INAMPEN = 1 << 10;
        const EXBUFEN = 1 << 9;
        const ADCCONVEN = 1 << 8;
        const ADCEN = 1 << 7;
        const DACEN = 1 << 6;
        const HSREFDIS = 1 << 5;
    }
}

bitflags! {
    // Waveform Generator Configuration Register
    // Address 0x00002014, Reset: 0x00000030, Name: WGCON
    pub struct WGCON: u32 {
        const reset         = 0x00000030;
        const DACGAINCAL    = 1 << 5;
        const DACOFFSETCAL  = 1 << 4;
        const TYPESEL_DAC   = 0b00 << 1; // Direct DAC
        const TYPESEL_SIN   = 0b10 << 1; // Sinusoidal
        const TYPESEL_TRA   = 0b11 << 1; // Trapezoidal
        const TRAPRSTEN     = 1;
    }
}

bitflags! {
    // Analog Generation Interrupt Register
    // Address 0x0000209C, Reset: 0x00000010, Name: AFEGENINTSTA
    pub struct AFEGENINTSTA: u32 {
        const CUSTOMINT3 = 1 << 3; // General-Purpose Custom Interrupt 3
        const CUSTOMINT2 = 1 << 2; // General-Purpose Custom Interrupt 2
        const CUSTOMINT1 = 1 << 1; // General-Purpose Custom Interrupt 1
        const CUSTOMINT0 = 1 << 0; // General-Purpose Custom Interrupt 0
    }
}

bitflags! {
    // DFT Configuration Register
    // Address 0x000020D0, Reset: 0x00000090, Name: DFTCON
    pub struct DFTCON: u32 {
        const DFTINSEL_SINC2            = 0b00 << 20;
        const DFTINSEL_GAIN_ANDOFFSET   = 0b01 << 20;
        const ADC_RAW                   = 0b10 << 20;
        const DFTNUM_4                  = 0b0000 << 4;
        const DFTNUM_8                  = 0b0001 << 4;
        const DFTNUM_16                 = 0b0010 << 4;
        const DFTNUM_32                 = 0b0011 << 4;
        const DFTNUM_64                 = 0b0100 << 4;
        const DFTNUM_128                = 0b0101 << 4;
        const DFTNUM_256                = 0b0110 << 4;
        const DFTNUM_512                = 0b0111 << 4;
        const DFTNUM_1024               = 0b1000 << 4;
        const DFTNUM_2048               = 0b1001 << 4;
        const DFTNUM_4096               = 0b1010 << 4;
        const DFTNUM_8192               = 0b1011 << 4;
        const DFTNUM_16384              = 0b1100 << 4;
        const HANNINGEN                 = 0b1 << 0;
    }
}

bitflags! {
    // HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER
    // Address 0x00002180, Reset 0x00000037, Name BEFSENCON
    
}

bitflags! {
    // ADC Configuration Register,
    // Address 0x000021A8, Reset: 0x00000000, Name: ADCCON
    pub struct ADCCON: u32 {
        const GNPGA_1_5    = 1 << 16;
        const MUXSELN_TIAN = 0b00001 << 8;
        const MUXSELN_TEMP = 0b01011 << 8;
        const MUXSELP_TIAP = 0b00001;
        const MUXSELP_TEMP = 0b01011;
    }
}