LUMC-bioz/bioz-firmware-rs
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Added external interrupt and test to determine impedance. Not working yet.

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Hubald Verzijl
2025-08-12 22:44:08 +02:00
parent 04b6083460
commit f1015ee00d
5 changed files with 162 additions and 23 deletions
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38
src/ad5940.rs
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@@ -207,8 +207,8 @@ impl AD5940 {
// info!("DATAFIFORD: 0x{:08X}", test);
// }
let test = self.read_reg_raw(0x2200).await.unwrap();
info!("FIFOCNTSTA: {}", (test>>16) & 0b111_1111_1111);
// let test = self.read_reg_raw(0x2200).await.unwrap();
// info!("FIFOCNTSTA: {}", (test>>16) & 0b111_1111_1111);
}
pub async fn afecon(&mut self, ctr: AFECON, state: bool) {
@@ -249,6 +249,22 @@ impl AD5940 {
let reg = self.read_reg(Register::SWCON).await.unwrap();
let mut reg = SWCON::from_bits_truncate(reg);
// T9CON
if ctr.contains(SWCON::T9CON) {
reg |= SWCON::T9CON;
} else {
reg &= !SWCON::T9CON;
}
// TMUXCON
if (ctr & SWCON::TMUXCON_MSK) == SWCON::TMUXCON_T2 {
reg &= !SWCON::TMUXCON_MSK;
reg |= SWCON::TMUXCON_T2;
} else if (ctr & SWCON::TMUXCON_MSK) == SWCON::TMUXCON_TR1 {
reg &= !SWCON::TMUXCON_MSK;
reg |= SWCON::TMUXCON_TR1;
}
// NMUXCON
if (ctr & SWCON::NMUXCON_MSK) == SWCON::NMUXCON_N2 {
reg &= !SWCON::NMUXCON_MSK;
@@ -256,7 +272,10 @@ impl AD5940 {
} else if (ctr & SWCON::NMUXCON_MSK) == SWCON::NMUXCON_N5 {
reg &= !SWCON::NMUXCON_MSK;
reg |= SWCON::NMUXCON_N5;
};
} else if (ctr & SWCON::NMUXCON_MSK) == SWCON::NMUXCON_NR1 {
reg &= !SWCON::NMUXCON_MSK;
reg |= SWCON::NMUXCON_NR1;
}
// PMUXCON
if (ctr & SWCON::PMUXCON_MSK) == SWCON::PMUXCON_P2 {
@@ -265,12 +284,18 @@ impl AD5940 {
} else if (ctr & SWCON::PMUXCON_MSK) == SWCON::PMUXCON_P11 {
reg &= !SWCON::PMUXCON_MSK;
reg |= SWCON::PMUXCON_P11;
} else if (ctr & SWCON::PMUXCON_MSK) == SWCON::PMUXCON_PR0 {
reg &= !SWCON::PMUXCON_MSK;
reg |= SWCON::PMUXCON_PR0;
}
// DMUXCON
if ctr.contains(SWCON::DMUXCON_D5) {
if (ctr & SWCON::DMUXCON_MSK) == SWCON::DMUXCON_D5 {
reg &= !SWCON::DMUXCON_MSK;
reg |= SWCON::DMUXCON_D5;
} else if { ctr & SWCON::DMUXCON_MSK } == SWCON::DMUXCON_DR0 {
reg &= !SWCON::DMUXCON_MSK;
reg |= SWCON::DMUXCON_DR0;
}
self.write_reg(Register::SWCON, reg.bits()).await.unwrap();
@@ -397,7 +422,7 @@ impl AD5940 {
| SWCON::PMUXCON_P11
| SWCON::DMUXCON_D5).await;
//
self.write_reg_raw(0x0000_20D0, 0b1000 << 4).await.unwrap();
self.write_reg_raw(0x0000_20D0, 0b1000 << 4).await.unwrap(); // 1024 OSR
// SINC3 = 5 --> 160000 Hz
// SINC2 = 178 --> 898,8764044944Hz
// ... (DFTNUM = 2048)
@@ -452,4 +477,7 @@ pub enum Register {
SEQTIMEOUT = 0x0000_2068, // Sequencer Timeout Counter Register
SEQCRC = 0x0000_2060, // Sequencer CRC Value Register
DATAFIFOTHRES = 0x0000_21E0, // Data FIFO Threshold Register
SYNCEXTDEVICE = 0x0000_2054, // Sync External Device Register
GP0CON = 0x0000_0000, // GPIO Port 0 Configuration Register
DATAFIFORD = 0x0000_206C, // Data FIFO Read Register
}