Created new impedance file for impedance_setup.

src/ad5940.rs

@@ -1,6 +1,5 @@
 use defmt::*;
 
-use embassy_embedded_hal::shared_bus::asynch::spi;
 use embassy_stm32::{gpio::Output, mode::Blocking, spi::Spi, spi::Error};
 use embassy_time::Timer;
 
@@ -410,6 +409,56 @@ impl AD5940 {
         }
     }
 
+    pub async fn sequencer_calculate_wait_time(&mut self, config: &DspConfig) -> Option<u32> {
+        let mut wait_time = 0;
+
+        let sinc3_table = [5, 4, 2];
+        let sinc2_table = [22, 44, 89, 178, 267, 533, 640, 667, 800, 889, 1067, 1333];
+
+        match config.dftin {
+            Some(DFTINSEL::Sinc2) => {
+                if let Some(sinc3osr) = config.sinc3osr {
+                    wait_time += sinc3_table[sinc3osr as usize];
+                } else {
+                    return None; // Sinc2 requires sinc3osr to be set
+                };
+
+                if let Some(sinc2osr) = config.sinc2osr {
+                    wait_time += sinc2_table[sinc2osr as usize];
+                } else {
+                    return None; // Sinc2 requires sinc2osr to be set
+                };
+            }
+            Some(DFTINSEL::GainOffset) => {
+                if let Some(sinc3osr) = config.sinc3osr {
+                    wait_time += sinc3_table[sinc3osr as usize];
+                } else {
+                    return None; // Sinc2 requires sinc3osr to be set
+                };
+            }
+            Some(DFTINSEL::AdcRaw) => {
+            }
+            None => {
+                return None;
+            }
+        }
+
+        // Calculate wait time based on DFTNUM
+        if let Some(dftnum) = config.dftnum {
+            let samples_per_dft = 1 << (dftnum as u32 + 2);
+            wait_time *= samples_per_dft;
+        } else {
+            return None; // DFTNUM must be set
+        }
+
+        // When ACLK = 16MHz, ADC samplerate is 800kHz
+        // When ACLK = 32MHz, ADC samplerate is 1.6MHz
+        // --> Always per ADC sample 20 cycles
+        wait_time *= 20;
+
+        Some(wait_time)
+    }
+
     pub async fn apply_switch_config(&mut self, config: SwitchConfig) -> Result<(), Error> {
         // SWCON
         let mut current = self.read_reg(Register::SWCON).await?;
@@ -444,7 +493,7 @@ impl AD5940 {
         Ok(())
     }
 
-    pub async fn apply_dsp_config(&mut self, config: DspConfig) -> Result<(), Error> {
+    pub async fn apply_dsp_config(&mut self, config: &DspConfig) -> Result<(), Error> {
         // ADCCON
         let mut current = self.read_reg(Register::ADCCON).await?;
 
@@ -454,7 +503,7 @@ impl AD5940 {
         }
         if let Some(muxselp) = config.muxselp {
             current &= !(0b11111);
-            current |= muxselp as u32;
+            current |= (muxselp as u32);
         }
 
         self.write_reg(Register::ADCCON, current).await?;
@@ -652,42 +701,6 @@ impl AD5940 {
 
         Ok(())
     }
-
-    pub async fn init_impedance(&mut self) -> Result<(), Error> {
-        // AFECON:
-        self.afecon(
-            AFECON::DACBUFEN
-            | AFECON::DACREFEN
-            | AFECON::SINC2EN
-            | AFECON::TIAEN
-            | AFECON::INAMPEN
-            | AFECON::EXBUFEN
-            | AFECON::DACEN,
-            true,
-        )
-        .await;
-
-        // Set DSP configuration
-        let dsp_config = DspConfig::default()
-            .adc_mux_n(MUXSELN::HsTiaNeg)
-            .adc_mux_p(MUXSELP::HsTiaPos)
-            .ctiacon(CTIACON::C32)
-            .rtiacon(RTIACON::R5k)
-            .sinc3osr(SINC3OSR::R5)
-            .sinc2osr(SINC2OSR::R178)
-            .adcsamplerate(ADCSAMPLERATE::R800Hz)
-            .dftin_sel(DFTINSEL::GainOffset)
-            .dftnum(DFTNUM::Num2048)
-            .hanning(true);
-
-        self.apply_dsp_config(dsp_config).await.unwrap();
-
-        // WGCON: set sinus output
-        let config_wgcon = WGCON::TYPESEL_SIN.bits();
-        self.write_reg(Register::WGCON, config_wgcon).await.unwrap();
-
-        Ok(())
-    }
 }
 
 #[allow(dead_code)]