Updated library.

src/ad5940_registers.rs

@@ -1,9 +1,27 @@
 use bitflags::bitflags;
 
 #[allow(dead_code)]
-pub trait Resettable {
+pub trait RegisterField {
+    /// Reset value for this field
     fn reset() -> Self;
-    // fn msk() -> u32;
+
+    /// Bit offset of the field within the register
+    const BIT_OFFSET: u32;
+
+    /// Bitmask of the field (not shifted)
+    const MASK: u32;
+
+    /// Clears the field bits in the register
+    fn clear(reg: u32) -> u32 {
+        reg & !(Self::MASK << Self::BIT_OFFSET)
+    }
+
+    /// Applies a new value to the field in the register
+    fn apply(reg: u32, val: u32) -> u32 {
+        let cleared = reg & !(Self::MASK << Self::BIT_OFFSET);
+        let shifted = (val & Self::MASK) << Self::BIT_OFFSET;
+        cleared | shifted
+    }
 }
 
 #[allow(dead_code)]
@@ -12,13 +30,12 @@ pub enum T9CON {
     T9Open = 0,
 }
 
-impl Resettable for T9CON {
+impl RegisterField for T9CON {
     fn reset() -> Self {
         T9CON::T9Open
     }
-    // fn msk() -> u32 {
-        // 0b1
-    // }
+    const BIT_OFFSET: u32 = 17;
+    const MASK: u32 = 0b1;
 }
 
 #[allow(dead_code)]
@@ -35,10 +52,12 @@ pub enum TMUXCON {
     AllClosed = 0b1001,
 }
 
-impl Resettable for TMUXCON {
+impl RegisterField for TMUXCON {
     fn reset() -> Self {
         TMUXCON::AllOpen
     }
+    const BIT_OFFSET: u32 = 12;
+    const MASK: u32 = 0b1111;
 }
 
 #[allow(dead_code)]
@@ -57,10 +76,12 @@ pub enum NMUXCON {
     AllOpen = 0b1111,
 }
 
-impl Resettable for NMUXCON {
+impl RegisterField for NMUXCON {
     fn reset() -> Self {
         NMUXCON::AllOpen
     }
+    const BIT_OFFSET: u32 = 8;
+    const MASK: u32 = 0b1111;
 }
 
 #[allow(dead_code)]
@@ -79,10 +100,12 @@ pub enum PMUXCON {
     AllOpen = 0b1111,
 }
 
-impl Resettable for PMUXCON {
+impl RegisterField for PMUXCON {
     fn reset() -> Self {
         PMUXCON::AllOpen
     }
+    const BIT_OFFSET: u32 = 4;
+    const MASK: u32 = 0b1111;
 }
 
 #[allow(dead_code)]
@@ -99,10 +122,12 @@ pub enum DMUXCON {
     AllClosed = 0b1001
 }
 
-impl Resettable for DMUXCON {
+impl RegisterField for DMUXCON {
     fn reset() -> Self {
         DMUXCON::AllOpen
     }
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b1111;
 }
 
 #[allow(dead_code)]
@@ -110,19 +135,37 @@ impl Resettable for DMUXCON {
 #[derive(Copy, Clone)]
 pub enum MUXSELN 
 {
+    Floating = 0b00000,
     HsTiaNeg = 0b00001,
     LpTiaNeg = 0b00010,
     AIN1    = 0b00101,
 }
 
+impl RegisterField for MUXSELN {
+    fn reset() -> Self {
+        MUXSELN::Floating
+    }
+    const BIT_OFFSET: u32 = 8;
+    const MASK: u32 = 0b11111;
+}
+
 #[allow(dead_code)]
 #[repr(u32)]
 #[derive(Copy, Clone)]
 pub enum MUXSELP {
+    Floating = 0b00000,
     HsTiaPos = 0b00001,
     AIN1    = 0b00101,
 }
 
+impl RegisterField for MUXSELP {
+    fn reset() -> Self {
+        MUXSELP::Floating
+    }
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b11111;
+}
+
 #[allow(dead_code)]
 #[repr(u32)]
 #[derive(Copy, Clone)]
@@ -132,10 +175,12 @@ pub enum DFTINSEL {
     AdcRaw      = 0b10
 }
 
-impl Resettable for DFTINSEL {
+impl RegisterField for DFTINSEL {
     fn reset() -> Self {
         DFTINSEL::Sinc2
     }
+    const BIT_OFFSET: u32 = 20;
+    const MASK: u32 = 0b11;
 }
 
 #[allow(dead_code)]
@@ -157,10 +202,28 @@ pub enum DFTNUM {
     Num16384   = 0b1100,
 }
 
-impl Resettable for DFTNUM {
+impl RegisterField for DFTNUM {
     fn reset() -> Self {
         DFTNUM::Num2048
     }
+    const BIT_OFFSET: u32 = 4;
+    const MASK: u32 = 0b1111;
+}
+
+#[allow(dead_code)]
+#[repr(u32)]
+#[derive(Copy, Clone)]
+pub enum HANNING {
+    Disable = 0,
+    Enable = 1,
+}
+
+impl RegisterField for HANNING {
+    fn reset() -> Self {
+        HANNING::Disable
+    }
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b1;
 }
 
 #[allow(dead_code)]
@@ -174,10 +237,12 @@ pub enum CTIACON {
     C32 = 1 << 4,
 }
 
-impl Resettable for CTIACON {
+impl RegisterField for CTIACON {
     fn reset() -> Self {
         CTIACON::C1
     }
+    const BIT_OFFSET: u32 = 5;
+    const MASK: u32 = 0b111_1111;
 }
 
 #[allow(dead_code)]
@@ -194,10 +259,12 @@ pub enum RTIACON {
     Open = 0b1111,
 }
 
-impl Resettable for RTIACON {
+impl RegisterField for RTIACON {
     fn reset() -> Self {
         RTIACON::Open
     }
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b1111;
 }
 
 #[allow(dead_code)]
@@ -208,10 +275,12 @@ pub enum SINC3OSR {
     R2 = 0b10,
 }
 
-impl Resettable for SINC3OSR {
+impl RegisterField for SINC3OSR {
     fn reset() -> Self {
         SINC3OSR::R5
     }
+    const BIT_OFFSET: u32 = 12;
+    const MASK: u32 = 0b11;
 }
 
 #[allow(dead_code)]
@@ -231,10 +300,12 @@ pub enum SINC2OSR {
     R1333 = 0b1011,
 }
 
-impl Resettable for SINC2OSR {
+impl RegisterField for SINC2OSR {
     fn reset() -> Self {
         SINC2OSR::R178
     }
+    const BIT_OFFSET: u32 = 8;
+    const MASK: u32 = 0b1111;
 }
 
 #[allow(dead_code)]
@@ -244,10 +315,109 @@ pub enum ADCSAMPLERATE {
     R1_6MHz = 0,
 }
 
-impl Resettable for ADCSAMPLERATE {
+impl RegisterField for ADCSAMPLERATE {
     fn reset() -> Self {
         ADCSAMPLERATE::R1_6MHz
     }
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b1;
+}
+
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub enum DATAMEMMDE {
+    FIFOMode = 0b10,
+    Stream = 0b11,
+}
+
+impl RegisterField for DATAMEMMDE {
+    fn reset() -> Self {
+        DATAMEMMDE::FIFOMode
+    }
+    const BIT_OFFSET: u32 = 9;
+    const MASK: u32 = 0b11;
+}
+
+#[allow(dead_code, non_camel_case_types)]
+#[derive(Copy, Clone)]
+pub enum DATA_MEM_SEL {
+    Reserved = 0b000,
+    Size2kB = 0b001,
+    Size4kB = 0b010,
+    Size6kB = 0b011,
+}
+
+impl RegisterField for DATA_MEM_SEL {
+    fn reset() -> Self {
+        DATA_MEM_SEL::Reserved
+    }
+    const BIT_OFFSET: u32 = 6;
+    const MASK: u32 = 0b111;
+}
+
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub enum CMDMEMMDE {
+    MemoryMode = 0b01,
+    Reserved = 0b10,
+}
+
+impl RegisterField for CMDMEMMDE {
+    fn reset() -> Self {
+        CMDMEMMDE::Reserved
+    }
+    const BIT_OFFSET: u32 = 3;
+    const MASK: u32 = 0b111;
+}
+
+#[allow(dead_code, non_camel_case_types)]
+#[derive(Copy, Clone)]
+pub enum CMD_MEM_SEL {
+    Reserved = 0x0,
+    Size2kB = 0x1,
+    Size4kB = 0x2,
+    Size6kB = 0x3,
+}
+
+impl RegisterField for CMD_MEM_SEL {
+    fn reset() -> Self {
+        CMD_MEM_SEL::Reserved
+    }
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b111;
+}
+
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum DATAFIFOSRCSEL {
+    ADC = 0b000,
+    DFT = 0b010,
+    Sinc2 = 0b011,
+    Variance = 0b100,
+    Mean = 0b101,
+}
+
+impl RegisterField for DATAFIFOSRCSEL {
+    fn reset() -> Self {
+        DATAFIFOSRCSEL::ADC
+    }
+    const BIT_OFFSET: u32 = 13;
+    const MASK: u32 = 0b111;
+}
+
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum DATAFIFOEN {
+    FIFOisReset = 0b0,
+    Normal = 0b1,
+}
+
+impl RegisterField for DATAFIFOEN {
+    fn reset() -> Self {
+        DATAFIFOEN::FIFOisReset
+    }
+    const BIT_OFFSET: u32 = 11;
+    const MASK: u32 = 0b1;
 }
 
 bitflags! {