LUMC-bioz/bioz-firmware-rs
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Updated library.

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This commit is contained in:
Hubald Verzijl
2025-08-18 14:49:58 +02:00
parent eaeff4f527
commit d17ef6c7ae
5 changed files with 346 additions and 116 deletions
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156
src/ad5940.rs
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@@ -18,10 +18,6 @@ pub struct SwitchConfig {
}
impl SwitchConfig {
pub fn new() -> Self {
Self::default()
}
pub fn t9con(mut self, t9con: T9CON) -> Self {
self.t9con = Some(t9con);
self
@@ -64,10 +60,6 @@ pub struct DspConfig {
}
impl DspConfig {
pub fn new() -> Self {
Self::default()
}
pub fn adc_mux_n(mut self, muxseln: MUXSELN) -> Self {
self.muxseln = Some(muxseln);
self
@@ -119,6 +111,43 @@ impl DspConfig {
}
}
#[allow(dead_code)]
#[derive(Default)]
pub struct SramConfig {
datafifosrcsel: Option<DATAFIFOSRCSEL>,
datafifoen: Option<DATAFIFOEN>,
data_mem_size: Option<DATA_MEM_SEL>,
cmd_mem_mode: Option<CMDMEMMDE>,
cmd_mem_size: Option<CMD_MEM_SEL>,
}
impl SramConfig {
pub fn datafifosrcsel(mut self, datafifosrcsel: DATAFIFOSRCSEL) -> Self {
self.datafifosrcsel = Some(datafifosrcsel);
self
}
pub fn datafifoen(mut self, datafifoen: DATAFIFOEN) -> Self {
self.datafifoen = Some(datafifoen);
self
}
pub fn data_size(mut self, data_mem_size: DATA_MEM_SEL) -> Self {
self.data_mem_size = Some(data_mem_size);
self
}
pub fn cmd_mode(mut self, cmd_mem_mode: CMDMEMMDE) -> Self {
self.cmd_mem_mode = Some(cmd_mem_mode);
self
}
pub fn cmd_size(mut self, cmd_mem_size: CMD_MEM_SEL) -> Self {
self.cmd_mem_size = Some(cmd_mem_size);
self
}
}
pub struct Sequencer {
}
@@ -464,28 +493,23 @@ impl AD5940 {
let mut current = self.read_reg(Register::SWCON).await?;
if let Some(t9con) = config.t9con {
current &= !(0b1 << 17);
current |= (t9con as u32) << 17;
current = T9CON::apply(current, t9con as u32);
}
if let Some(tmuxcon) = config.tmuxcon {
current &= !(0b1111 << 12);
current |= (tmuxcon as u32) << 12;
current = TMUXCON::apply(current, tmuxcon as u32);
}
if let Some(nmuxcon) = config.nmuxcon {
current &= !(0b1111 << 8);
current |= (nmuxcon as u32) << 8;
current = NMUXCON::apply(current, nmuxcon as u32);
}
if let Some(pmuxcon) = config.pmuxcon {
current &= !(0b1111 << 4);
current |= (pmuxcon as u32) << 4;
current = PMUXCON::apply(current, pmuxcon as u32);
}
if let Some(dmuxcon) = config.dmuxcon {
current &= !(0b1111);
current |= dmuxcon as u32;
current = DMUXCON::apply(current, dmuxcon as u32);
}
self.write_reg(Register::SWCON, current).await?;
@@ -498,12 +522,10 @@ impl AD5940 {
let mut current = self.read_reg(Register::ADCCON).await?;
if let Some(muxseln) = config.muxseln {
current &= !(0b11111 << 8);
current |= (muxseln as u32) << 8;
current = MUXSELN::apply(current, muxseln as u32);
}
if let Some(muxselp) = config.muxselp {
current &= !(0b11111);
current |= (muxselp as u32);
current = MUXSELP::apply(current, muxselp as u32);
}
self.write_reg(Register::ADCCON, current).await?;
@@ -512,13 +534,11 @@ impl AD5940 {
let mut current = self.read_reg(Register::HSRTIACON).await?;
if let Some(ctiacon) = config.ctiacon {
current &= !(0b1111 << 5);
current |= (ctiacon as u32) << 5;
current = CTIACON::apply(current, ctiacon as u32);
}
if let Some(rtiacon) = config.rtiacon {
current &= !(0b1111);
current |= rtiacon as u32;
current = RTIACON::apply(current, rtiacon as u32);
}
self.write_reg(Register::HSRTIACON, current).await?;
@@ -527,18 +547,15 @@ impl AD5940 {
let mut current = self.read_reg(Register::ADCFILTERCON).await?;
if let Some(sinc3osr) = config.sinc3osr{
current &= !(0b11 << 12);
current |= (sinc3osr as u32) << 12;
current = SINC3OSR::apply(current, sinc3osr as u32);
}
if let Some(sinc2osr) = config.sinc2osr {
current &= !(0b1111 << 8);
current |= (sinc2osr as u32) << 8;
current = SINC2OSR::apply(current, sinc2osr as u32);
}
if let Some(adcsamplerate) = config.adcsamplerate {
current &= !1;
current |= adcsamplerate as u32;
current = ADCSAMPLERATE::apply(current, adcsamplerate as u32);
}
self.write_reg(Register::ADCFILTERCON, current).await?;
@@ -547,16 +564,13 @@ impl AD5940 {
let mut current = self.read_reg(Register::DFTCON).await?;
if let Some(dftin) = config.dftin {
current &= !(0b11 << 20);
current |= (dftin as u32) << 20;
current = DFTINSEL::apply(current, dftin as u32);
}
if let Some(dftnum) = config.dftnum {
current &= !(0b1111 << 4);
current |= (dftnum as u32) << 4;
current = DFTNUM::apply(current, dftnum as u32);
}
if let Some(hanning) = config.hanning {
current &= !(0b1 << 0);
current |= (hanning as u32) << 0;
current = HANNING::apply(current, hanning as u32);
}
self.write_reg(Register::DFTCON, current).await?;
@@ -603,30 +617,42 @@ impl AD5940 {
self.write_reg(Register::WGFCW, sinefcw).await.unwrap();
}
pub async fn cmddatacon(&mut self) {
pub async fn apply_sram_config(&mut self, config: SramConfig) -> Result<(), Error> {
// Disable sequencer
let mut reg = self.read_reg(Register::SEQCON).await.unwrap();
reg &= !0x0000_0001; // Clear the enable bits
self.write_reg(Register::SEQCON, reg).await.unwrap();
self.write_reg(Register::SEQCON, 0x0000_0002).await?;
// Reset SEQCON
self.write_reg(Register::SEQCNT, 0x0000_0001).await.unwrap();
self.write_reg(Register::SEQCNT, 0x0000_0001).await?;
// Disable fifo
self.write_reg(Register::FIFOCON, 0b010 << 13).await.unwrap();
// self.write_reg(Register::FIFOCON, 0b011 << 13).await.unwrap();
// FIFICON
let mut current_fifocon = self.read_reg(Register::FIFOCON).await?;
if let Some(datafifosrcsel) = config.datafifosrcsel {
current_fifocon = DATAFIFOSRCSEL::apply(current_fifocon, datafifosrcsel as u32);
}
current_fifocon &= !(0b1 << 11); // Disable FIFO
self.write_reg(Register::FIFOCON, current_fifocon).await?;
let cmd = 0b101 << 9 | 0b001 << 6 | 0b01 << 3 | 0b01;
self.write_reg(Register::CMDDATACON, cmd).await.unwrap();
// CMDDATACON
let mut current = self.read_reg(Register::CMDDATACON).await?;
if let Some(size) = config.data_mem_size {
current = DATA_MEM_SEL::apply(current, size as u32);
}
if let Some(mode) = config.cmd_mem_mode {
current = CMDMEMMDE::apply(current, mode as u32);
}
if let Some(size) = config.cmd_mem_size {
current = CMD_MEM_SEL::apply(current, size as u32);
}
self.write_reg(Register::CMDDATACON, current).await?;
// Enable FIFO
self.write_reg(Register::FIFOCON, 0b010 << 13 | 1 << 11 ).await.unwrap();
// self.write_reg(Register::FIFOCON, 0b011 << 13 | 1 << 11 ).await.unwrap();
current_fifocon |= 0b1 << 11; // Enable FIFO
self.write_reg(Register::FIFOCON, current_fifocon).await?;
// Enable sequencer
let mut reg = self.read_reg(Register::SEQCON).await.unwrap();
reg |= 0x0000_0001; // Set the enable bit
self.write_reg(Register::SEQCON, reg).await.unwrap();
self.write_reg(Register::SEQCON, 0x0000_0003).await?;
Ok(())
}
pub async fn get_chipid(&mut self) -> u16 {
@@ -682,7 +708,7 @@ impl AD5940 {
self.write_reg(Register::WGCON, config_wgcon).await?;
// SWCON - set up switch matri
let switch_config = SwitchConfig::new()
let switch_config = SwitchConfig::default()
.nmuxcon(NMUXCON::N2Closed)
.pmuxcon(PMUXCON::P11Closed)
.dmuxcon(DMUXCON::D5Closed);
@@ -705,8 +731,6 @@ impl AD5940 {
#[allow(dead_code)]
#[allow(non_camel_case_types)]
#[repr(u8)]
enum Command {
SPICMD_SETADDR = 0x20,
@@ -722,9 +746,9 @@ enum Command {
pub enum Register {
ADIID = 0x0000_0400, // Analog Devices Inc., identification register
CHIPID = 0x0000_0404, // Chip identification register
TRIGSEQ = 0x0000_0430, // Trigger Sequencer Register
TRIGSEQ = 0x0000_0430, // Trigger Sequencer Register
AFECON = 0x0000_2000, // Configuration Register
SEQCON = 0x0000_2004, // Sequencer Configuration Register
SEQCON = 0x0000_2004, // Sequencer Configuration Register
FIFOCON = 0x0000_2008, // FIFO Configuration Register
SWCON = 0x0000_200C, // Switch Matrix Configuration Register
WGCON = 0x0000_2014, // Waveform Generator Configuration Register
@@ -739,7 +763,7 @@ pub enum Register {
SEQ0INFO = 0x0000_21CC, // Sequence 0 Information Register
SEQ1INFO = 0x0000_21E8, // Sequence 1 Information Register
SEQ2INFO = 0x0000_21D0, // Sequence 2 Information Register
CMDDATACON = 0x0000_21D8, // Command Data Control Register
CMDDATACON = 0x0000_21D8, // Command Data Control Register
SEQ3INFO = 0x0000_21E4, // Sequence 3 Information Register
AFEGENINTSTA = 0x0000_209C, // Analog Generation Interrupt Register
CMDFIFOWADDR = 0x0000_21D4, // Command FIFO Write Address Register
@@ -751,12 +775,12 @@ pub enum Register {
SEQCRC = 0x0000_2060, // Sequencer CRC Value Register
DATAFIFOTHRES = 0x0000_21E0, // Data FIFO Threshold Register
SYNCEXTDEVICE = 0x0000_2054, // Sync External Device Register
GP0CON = 0x0000_0000, // GPIO Port 0 Configuration Register
DATAFIFORD = 0x0000_206C, // Data FIFO Read Register
DFTCON = 0x0000_20D0, // DFT Configuration Register
HSDACCON = 0x0000_2010, // High Speed DAC Configuration Register
HSRTIACON = 0x0000_20F0, // High Speed RTIA Configuration Register
BUFSENCON = 0x0000_2180, // HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER
FIFOCNTSTA = 0x0000_2200, // Command and data FIFO internal data count register
GP0CON = 0x0000_0000, // GPIO Port 0 Configuration Register
DATAFIFORD = 0x0000_206C, // Data FIFO Read Register
DFTCON = 0x0000_20D0, // DFT Configuration Register
HSDACCON = 0x0000_2010, // High Speed DAC Configuration Register
HSRTIACON = 0x0000_20F0, // High Speed RTIA Configuration Register
BUFSENCON = 0x0000_2180, // HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER
FIFOCNTSTA = 0x0000_2200, // Command and data FIFO internal data count register
ADCFILTERCON = 0x0000_2044 // ADC Output Filters Configuration Register
}