Added clk config part, increased ADC clk to 32MHz.

src/ad5940_registers.rs

@@ -420,6 +420,128 @@ impl RegisterField for DATAFIFOEN {
     const MASK: u32 = 0b1;
 }
 
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum ADCCLKDIV {
+    DIV1 = 0b01,
+    DIV2 = 0b10,
+}
+
+impl RegisterField for ADCCLKDIV {
+    fn reset() -> Self {
+        Self::DIV1
+    }
+    const BIT_OFFSET: u32 = 6;
+    const MASK: u32 = 0b1111;
+}
+
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum SYSCLKDIV {
+    DIV1 = 1,
+    DIV2,
+    DIV3,
+    DIV4,
+    DIV5,
+    DIV6,
+    DIV7,
+    DIV8,
+    DIV9,
+    DIV10,
+    DIV11,
+    DIV12,
+    DIV13,
+    DIV14,
+    DIV15,
+    DIV16,
+    DIV17,
+    DIV18,
+    DIV19,
+    DIV20,
+    DIV21,
+    DIV22,
+    DIV23,
+    DIV24,
+    DIV25,
+    DIV26,
+    DIV27,
+    DIV28,
+    DIV29,
+    DIV30,
+    DIV31,
+}
+
+impl TryFrom<u8> for SYSCLKDIV {
+    type Error = &'static str;
+
+    fn try_from(value: u8) -> Result<Self, Self::Error> {
+        match value {
+            1 => Ok(SYSCLKDIV::DIV1),
+            2 => Ok(SYSCLKDIV::DIV2),
+            3 => Ok(SYSCLKDIV::DIV3),
+            4 => Ok(SYSCLKDIV::DIV4),
+            5 => Ok(SYSCLKDIV::DIV5),
+            6 => Ok(SYSCLKDIV::DIV6),
+            7 => Ok(SYSCLKDIV::DIV7),
+            8 => Ok(SYSCLKDIV::DIV8),
+            9 => Ok(SYSCLKDIV::DIV9),
+            10 => Ok(SYSCLKDIV::DIV10),
+            11 => Ok(SYSCLKDIV::DIV11),
+            12 => Ok(SYSCLKDIV::DIV12),
+            13 => Ok(SYSCLKDIV::DIV13),
+            14 => Ok(SYSCLKDIV::DIV14),
+            15 => Ok(SYSCLKDIV::DIV15),
+            16 => Ok(SYSCLKDIV::DIV16),
+            17 => Ok(SYSCLKDIV::DIV17),
+            18 => Ok(SYSCLKDIV::DIV18),
+            19 => Ok(SYSCLKDIV::DIV19),
+            20 => Ok(SYSCLKDIV::DIV20),
+            21 => Ok(SYSCLKDIV::DIV21),
+            22 => Ok(SYSCLKDIV::DIV22),
+            23 => Ok(SYSCLKDIV::DIV23),
+            24 => Ok(SYSCLKDIV::DIV24),
+            25 => Ok(SYSCLKDIV::DIV25),
+            26 => Ok(SYSCLKDIV::DIV26),
+            27 => Ok(SYSCLKDIV::DIV27),
+            28 => Ok(SYSCLKDIV::DIV28),
+            29 => Ok(SYSCLKDIV::DIV29),
+            30 => Ok(SYSCLKDIV::DIV30),
+            31 => Ok(SYSCLKDIV::DIV31),
+            _ => Err("Invalid SYSCLKDIV value"),
+        }
+    }
+}
+
+impl SYSCLKDIV {
+    pub fn div(value: u8) -> Self {
+        SYSCLKDIV::try_from(value).unwrap_or(SYSCLKDIV::DIV1)
+    }
+}
+
+impl RegisterField for SYSCLKDIV {
+    fn reset() -> Self {
+        SYSCLKDIV::DIV1
+    }
+
+    const BIT_OFFSET: u32 = 0;
+    const MASK: u32 = 0b1_1111;
+}
+
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum CLK32MHZEN  {
+    MHz32 = 0b0,
+    Mhz16 = 0b1,
+}
+
+impl RegisterField for CLK32MHZEN {
+    fn reset() -> Self {
+        CLK32MHZEN::Mhz16
+    }
+    const BIT_OFFSET: u32 = 2;
+    const MASK: u32 = 0b1;
+}
+
 bitflags! {
     // Configuration Register
     // Address 0x00002000, Reset: 0x00080000, Name: AFECON