Implemented fifo readout.

src/ad5940.rs

@@ -1,5 +1,6 @@
 use defmt::*;
 
+use embassy_embedded_hal::shared_bus::asynch::spi;
 use embassy_stm32::{gpio::Output, mode::Blocking, spi::Spi, spi::Error};
 use embassy_time::Timer;
 
@@ -237,6 +238,54 @@ impl AD5940 {
         Ok(())
     }
 
+    pub async fn read_fifo(&mut self, buf: &mut [u32]) -> Result<(), Error> {
+        if buf.len() < 3 {
+            self.cs.set_low();
+            self.spi.blocking_write(&[Command::SPICMD_SETADDR as u8])?;
+            self.spi.blocking_write(&[Register::DATAFIFORD as u16])?;
+            self.cs.set_high();
+
+            // Wait after cs is high
+            Timer::after_nanos(80).await;
+
+            for i in 0..buf.len() {
+                self.cs.set_low();
+                self.spi.blocking_write(&[Command::SPICMD_READREG as u8])?;//Write Host status/Don't care
+                self.spi.blocking_write(&[0 as u8])?;//Write Host status/Don't care
+                let mut byte = [0u32];
+                self.spi.blocking_read(&mut byte)?;
+                buf[i] = byte[0];
+                self.cs.set_high();
+
+                // Wait after cs is high
+                Timer::after_nanos(80).await;
+            }
+        } else  {
+            self.cs.set_low();
+            self.spi.blocking_write(&[Command::SPICMD_READFIFO as u8])?;
+            
+            // 6 dummy writes
+            for _ in 0..6 {
+                self.spi.blocking_write(&[0u8])?;
+            }
+
+            // Read all but last 2 elements
+            for i in 0..buf.len()-2 {
+                let mut byte = [0u32];
+                self.spi.blocking_read(&mut byte)?;
+                buf[i] = byte[0];                
+            }
+
+            // Read last 2 elements with transfer
+            let mut bytes = [0u32; 2];
+            self.spi.blocking_transfer(&mut bytes, &mut [0x4444_4444, 0x4444_4444])?;
+            buf[buf.len()-2] = bytes[0];
+            buf[buf.len()-1] = bytes[1];
+            self.cs.set_high();
+        }
+        Ok(())
+    }
+
     pub async fn system_init(&mut self) -> Result<(), Error> {
         // See table 14
         self.write_reg_raw(0x0908, 0x02C9).await?;
@@ -645,7 +694,7 @@ impl AD5940 {
 #[allow(non_camel_case_types)]
 
 
-
+#[repr(u8)]
 enum Command {
     SPICMD_SETADDR  = 0x20,
     SPICMD_READREG  = 0x6D,