LUMC-bioz/bioz-firmware-rs
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Added 4 lead-option for single frequency measurement.

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This commit is contained in:
Hubald Verzijl
2025-11-03 17:19:10 +01:00
parent 0859de24fb
commit 6358882a4c
4 changed files with 307 additions and 17 deletions
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31
src/ad5940_registers.rs
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@@ -130,6 +130,25 @@ impl RegisterField for DMUXCON {
const MASK: u32 = 0b1111;
}
#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
pub enum GNPGAIN {
Gain1 = 0b0,
Gain1_5 = 0b1,
Gain2 = 0b10,
Gain4 = 0b11,
Gain9 = 0b100,
}
impl RegisterField for GNPGAIN {
fn reset() -> Self {
GNPGAIN::Gain1
}
const BIT_OFFSET: u32 = 16;
const MASK: u32 = 0b111;
}
#[allow(dead_code)]
#[repr(u32)]
#[derive(Copy, Clone)]
@@ -138,7 +157,9 @@ pub enum MUXSELN
Floating = 0b00000,
HsTiaNeg = 0b00001,
LpTiaNeg = 0b00010,
AIN1 = 0b00101,
AIN1 = 0b00101,
AIN3 = 0b00111,
ExciNNode= 0b10100,
}
impl RegisterField for MUXSELN {
@@ -155,7 +176,11 @@ impl RegisterField for MUXSELN {
pub enum MUXSELP {
Floating = 0b00000,
HsTiaPos = 0b00001,
AIN1 = 0b00101,
AIN1 = 0b00101,
AIN2 = 0b00110,
AIN3 = 0b00111,
CE0 = 0b011001,
ExciPNode= 0b100100,
}
impl RegisterField for MUXSELP {
@@ -163,7 +188,7 @@ impl RegisterField for MUXSELP {
MUXSELP::Floating
}
const BIT_OFFSET: u32 = 0;
const MASK: u32 = 0b11111;
const MASK: u32 = 0b111111;
}
#[allow(dead_code)]