LUMC-bioz/bioz-firmware-rs
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Working sequencer.

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This commit is contained in:
Hubald Verzijl
2025-08-12 20:53:24 +02:00
parent 6b15a77cb5
commit 04b6083460
2 changed files with 93 additions and 84 deletions
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98
src/ad5940.rs
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@@ -45,8 +45,7 @@ impl AD5940 {
self.cs.set_high();
// Wait after cs is high
// Timer::after_nanos(80).await;
Timer::after_millis(10).await;
Timer::after_nanos(80).await;
// Read command
self.cs.set_low();
@@ -66,7 +65,6 @@ impl AD5940 {
// let mut data = [0u8; 5]; // First byte dummy, then four data bytes
// self.spi.blocking_read(&mut data)?;
self.cs.set_high();
Timer::after_millis(1).await;
Ok(result)
}
@@ -87,8 +85,7 @@ impl AD5940 {
self.cs.set_high();
// Wait after cs is high
// Timer::after_nanos(80).await;
Timer::after_millis(10).await;
Timer::after_nanos(80).await;
// Write value command
self.cs.set_low();
@@ -99,7 +96,6 @@ impl AD5940 {
self.spi.blocking_write(&[value as u16])?;
}
self.cs.set_high();
Timer::after_millis(1).await;
Ok(())
@@ -137,7 +133,7 @@ impl AD5940 {
if address as u32 > 0x21FF {
error!("Sequencer write address out of range: 0x{:04X}", address as u32);
}
let cmd = (((address as u32) >> 2) & 0x7F) << 24 | (value & 0xFF_FFFF);
let cmd = 0b1 << 31 | (((address as u32) >> 2) & 0x7F) << 24 | (value & 0xFF_FFFF);
self.sequencer_insert(cmd).await;
return Ok(())
@@ -148,7 +144,7 @@ impl AD5940 {
error!("Sequencer wait cycles out of range: {}", cycles);
return;
}
let cmd = 0b01 << 30 | 0x0000_0000 | cycles & 0x3FFF_FFFF;
let cmd = 0b00 << 30 | 0x0000_0000 | cycles & 0x3FFF_FFFF;
self.sequencer_insert(cmd).await;
}
@@ -174,12 +170,8 @@ impl AD5940 {
start_address &= 0x7FF; // Ensure start address is within bounds
while counter < self.seq_len {
self.write_reg(Register::CMDFIFOWADDR, start_address + (counter) as u32).await.unwrap();
Timer::after_millis(1).await;
self.write_reg(Register::CMDFIFOWADDR, start_address + counter as u32).await.unwrap();
self.write_reg(Register::CMDFIFOWRITE, self.seq_buffer[counter as usize]).await.unwrap();
// self.write_reg(Register::CMDFIFOWRITE, 0).await.unwrap();
Timer::after_millis(1).await;
// info!("{:032b}", self.seq_buffer[counter as usize]);
counter += 1;
}
}
@@ -198,40 +190,23 @@ impl AD5940 {
}
}
pub async fn sequencer_trigger(&mut self) {
pub async fn sequencer_trigger(&mut self, seq: u8) {
// Trigger the sequencer
self.write_reg(Register::TRIGSEQ, 1 << 0).await.unwrap();
// self.write_reg(Register::TRIGSEQ, 1 << 1).await.unwrap();
// self.write_reg(Register::TRIGSEQ, 1 << 2).await.unwrap();
// self.write_reg(Register::TRIGSEQ, 1 << 3).await.unwrap();
match seq {
0 => self.write_reg(Register::TRIGSEQ, 1 << 0).await.unwrap(),
1 => self.write_reg(Register::TRIGSEQ, 1 << 1).await.unwrap(),
2 => self.write_reg(Register::TRIGSEQ, 1 << 2).await.unwrap(),
3 => self.write_reg(Register::TRIGSEQ, 1 << 3).await.unwrap(),
_ => {
error!("Sequencers from 0 till 3 are allows, now: seq={}", seq);
},
}
// wait
// Timer::after_millis(10).await;
let test = self.read_reg(Register::SEQCNT).await.unwrap();
info!("Sequencer triggered, SEQCNT: {}", test);
let test = self.read_reg(Register::INTCFLAG0).await.unwrap();
info!("INTCFLAG0: 0x{:08X}", test);
let test = self.read_reg(Register::INTCFLAG1).await.unwrap();
info!("INTCFLAG1: 0x{:08X}", test);
self.write_reg_raw(0x3008, 0xFFFF_FFFF).await.unwrap();
self.write_reg_raw(0x300C, 0xFFFF_FFFF).await.unwrap();
let test = self.read_reg(Register::SEQTIMEOUT).await.unwrap();
info!("SEQTIMEOUT: {}", test);
let test = self.read_reg(Register::CMDFIFOWADDR).await.unwrap();
info!("CMDFIFOWADDR: {}", test);
// for i in 0..200 {
let test= self.read_reg_raw(0x206C).await.unwrap();
info!("DATAFIFORD: 0x{:08X}", test);
// for _ in 0..100 {
// let test = self.read_reg_raw(0x206C).await.unwrap();
// info!("DATAFIFORD: 0x{:08X}", test);
// }
let test = self.read_reg_raw(0x2200).await.unwrap();
info!("FIFOCNTSTA: {}", (test>>16) & 0b111_1111_1111);
}
@@ -314,12 +289,12 @@ impl AD5940 {
self.write_reg(Register::SEQCON, reg).await.unwrap();
// Reset SEQCON
self.write_reg(Register::SEQCNT, 0x0000_0002).await.unwrap();
self.write_reg(Register::SEQCNT, 0x0000_0001).await.unwrap();
// Disable fifo
self.write_reg(Register::FIFOCON, 0b010 << 13).await.unwrap();
let cmd = 0b10 << 9 | 0b001 << 6 | 1 << 3 | 1;
let cmd = 0b101 << 9 | 0b001 << 6 | 0b01 << 3 | 0b01;
self.write_reg(Register::CMDDATACON, cmd).await.unwrap();
// Enable FIFO
@@ -397,6 +372,37 @@ impl AD5940 {
Ok(())
}
pub async fn init_impedance(&mut self) -> Result<(), Error> {
// AFECON:
self.afecon(
AFECON::DACBUFEN
| AFECON::DACREFEN
| AFECON::SINC2EN
| AFECON::DFTEN
| AFECON::WAVEGENEN
| AFECON::TIAEN
| AFECON::INAMPEN
| AFECON::EXBUFEN
| AFECON::ADCCONVEN
| AFECON::ADCEN
| AFECON::DACEN,
true,
)
.await;
// SWCON - set up switch matrix for impedance measurement
self.swcon(
SWCON::NMUXCON_N2
| SWCON::PMUXCON_P11
| SWCON::DMUXCON_D5).await;
//
self.write_reg_raw(0x0000_20D0, 0b1000 << 4).await.unwrap();
// SINC3 = 5 --> 160000 Hz
// SINC2 = 178 --> 898,8764044944Hz
// ... (DFTNUM = 2048)
Ok(())
}
}
#[allow(dead_code)]