Added lineairmap to lib for sequencer.

src/ad5940.rs

@@ -3,6 +3,8 @@ use defmt::*;
 use embassy_stm32::{gpio::Output, mode::Blocking, spi::Spi, spi::Error};
 use embassy_time::Timer;
 
+use heapless::LinearMap;
+
 use crate::ad5940_registers::*;
 
 pub struct AD5940 {
@@ -11,7 +13,8 @@ pub struct AD5940 {
     rst: Output<'static>,
     seq_enabled: bool,
     pub seq_len: usize,
-    pub seq_buffer: [u32; 16],
+    pub seq_buffer: [u32; 25],
+    pub seq_gen_db: LinearMap<Register, u32, 16>,
 }
 
 impl AD5940 {
@@ -22,7 +25,8 @@ impl AD5940 {
             rst,
             seq_enabled: false,
             seq_len: 0,
-            seq_buffer: [0; 16],
+            seq_buffer: [0; 25],
+            seq_gen_db: LinearMap::new(),
         }
     }
 
@@ -34,7 +38,11 @@ impl AD5940 {
     }
 
     pub async fn read_reg(&mut self, address: Register) -> Result<u32, Error> {
-        self.read_reg_raw(address as u16).await
+        if self.seq_enabled {
+            self.sequencer_read_register(address).await
+        } else {
+            self.read_reg_raw(address as u16).await
+        }
     }
 
     pub async fn read_reg_raw(&mut self, address: u16) -> Result<u32, Error> {
@@ -129,10 +137,32 @@ impl AD5940 {
         }
     }
 
+    async fn sequencer_read_register(&mut self, address: Register) -> Result<u32, Error> {
+        if address as u32 > 0x21FF {
+            error!("Sequencer read address out of range: 0x{:04X}", address as u32);
+        }
+
+        // Read from sequencer database, if not present read default (often default) from hardware
+        if let Some(value) = self.seq_gen_db.get(&address) {
+            Ok(*value)
+        } else {
+            self.read_reg_raw(address as u16).await
+        }
+    }
+
     async fn sequencer_write_register(&mut self, address: Register, value: u32) -> Result<(), Error> {
         if address as u32 > 0x21FF {
             error!("Sequencer write address out of range: 0x{:04X}", address as u32);
         }
+
+        // Update or put in sequencer database
+        if self.seq_gen_db.contains_key(&address) {
+            *self.seq_gen_db.get_mut(&address).unwrap() = value;
+        } else {
+            self.seq_gen_db.insert(address, value).unwrap();
+        }
+
+        // Place into buffer
         let cmd = 0b1 << 31 | (((address as u32) >> 2) & 0x7F) << 24 | (value & 0xFF_FFFF);
         self.sequencer_insert(cmd).await;
 
@@ -154,7 +184,7 @@ impl AD5940 {
     }
 
     async fn sequencer_insert(&mut self, cmd: u32) {
-        if self.seq_len >= 16 {
+        if self.seq_len >= self.seq_buffer.len() {
             error!("Sequencer buffer full, cannot insert command: 0x{:08X}", cmd);
             return;
         }
@@ -263,7 +293,7 @@ impl AD5940 {
         } else if (ctr & SWCON::TMUXCON_MSK) == SWCON::TMUXCON_TR1 {
             reg &= !SWCON::TMUXCON_MSK;
             reg |= SWCON::TMUXCON_TR1;
-        }
+        } 
 
         // NMUXCON
         if (ctr & SWCON::NMUXCON_MSK) == SWCON::NMUXCON_N2 {
@@ -403,29 +433,43 @@ impl AD5940 {
         self.afecon(
             AFECON::DACBUFEN
             | AFECON::DACREFEN
-            | AFECON::SINC2EN
-            | AFECON::DFTEN
-            | AFECON::WAVEGENEN
+            // | AFECON::SINC2EN
+            // | AFECON::DFTEN
+            // | AFECON::WAVEGENEN
             | AFECON::TIAEN
             | AFECON::INAMPEN
             | AFECON::EXBUFEN
-            | AFECON::ADCCONVEN
-            | AFECON::ADCEN
+            // | AFECON::ADCCONVEN
+            // | AFECON::ADCEN
             | AFECON::DACEN,
             true,
         )
         .await;
 
         // SWCON - set up switch matrix for impedance measurement
-        self.swcon(
-            SWCON::NMUXCON_N2
-            | SWCON::PMUXCON_P11
-            | SWCON::DMUXCON_D5).await;
-        // 
-        self.write_reg_raw(0x0000_20D0, 0b1000 << 4).await.unwrap(); // 1024 OSR
+        // self.swcon(
+            // SWCON::NMUXCON_N2
+            // | SWCON::PMUXCON_P11
+            // | SWCON::DMUXCON_D5).await;
+
+        let config_wgcon = WGCON::TYPESEL_SIN.bits();
+        self.write_reg(Register::WGCON, config_wgcon).await.unwrap();
+
+        // BUFSENCON
+        self.write_reg(Register::BUFSENCON, 0b1).await.unwrap();
+
+        // DFTCON
+        self.write_reg(Register::DFTCON, 0b0111 << 4 | 0b1).await.unwrap(); // 1024 OSR
         // SINC3 = 5 --> 160000 Hz
         // SINC2 = 178 --> 898,8764044944Hz
         // ... (DFTNUM = 2048)
+
+        // ADCCON
+        self.write_reg(Register::ADCCON, ADCCON::MUXSELN_TIAN.bits() | ADCCON::MUXSELP_TIAP.bits()).await?;
+
+        // HSRTIACON: RTIACON 32pF & 5k 
+        self.write_reg(Register::HSRTIACON, 0b10000 << 5 | 0b0010).await?;
+
         Ok(())
     }
 }
@@ -445,7 +489,7 @@ enum Command {
 #[allow(dead_code)]
 #[allow(non_camel_case_types)]
 #[repr(u16)]
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Eq, PartialEq, Debug, defmt::Format)]
 pub enum Register {
     ADIID       = 0x0000_0400, // Analog Devices Inc., identification register
     CHIPID      = 0x0000_0404, // Chip identification register
@@ -480,4 +524,8 @@ pub enum Register {
     SYNCEXTDEVICE = 0x0000_2054, // Sync External Device Register
     GP0CON     = 0x0000_0000, // GPIO Port 0 Configuration Register
     DATAFIFORD = 0x0000_206C, // Data FIFO Read Register
-}
+    DFTCON     = 0x0000_20D0, // DFT Configuration Register
+    HSDACCON   = 0x0000_2010, // High Speed DAC Configuration Register
+    HSRTIACON  = 0x0000_20F0, // High Speed RTIA Configuration Register
+    BUFSENCON  = 0x0000_2180, // HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER
+}